Xilinx ISE WebPACK - Debian

Xilinx: ISE WebPACK

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local links: e1, vm4,

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History

2018-10-28: vm4 - ISE - since impact doesn't start from the menu I created a run_impact.sh file:

tingo@kg-vm4:~$ cat ~/progs/xilinx/14.7/14.7/ISE_DS/run_impact.sh
#!/bin/bash
. /home/tingo/progs/xilinx/14.7/14.7/ISE_DS/settings64.sh
impact

and now I can start impact from a 'ssh -X' session, like this:

tingo@kg-vm4:~$ ~/progs/xilinx/14.7/14.7/ISE_DS/run_impact.sh

good.

2018-10-28: vm4 - ISE - impact doesn't start from the menu, I just get this error message

_impact4: cannot connect to X server localhost:10.0

ok.

2018-09-11: vm4 - ISE - test it - I used the "Switches_LEDs" project as a test case. It works. Console output:

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -filter "/zs/personal/projects/fpga/xilinx/Switches_LEDs/iseconfig/filter.filter" -ifn "/zs/personal/projects/fpga/xilinx/Switches_LEDs/Switches_LEDs.xst" -ofn "/zs/personal/projects/fpga/xilinx/Switches_LEDs/Switches_LEDs.syr"
Reading design: Switches_LEDs.prj

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "/zs/personal/projects/fpga/xilinx/Switches_LEDs/Switches_LEDs.vhd" into library work
Parsing entity <Switches_LEDs>.
Parsing architecture <Behavioral> of entity <switches_leds>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <Switches_LEDs> (architecture <Behavioral>) from library <work>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <Switches_LEDs>.
    Related source file is "/zs/personal/projects/fpga/xilinx/Switches_LEDs/Switches_LEDs.vhd".
    Summary:
    no macro.
Unit <Switches_LEDs> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <Switches_LEDs> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block Switches_LEDs, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 4.372ns

=========================================================================

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -filter "iseconfig/filter.filter" -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 Switches_LEDs.ngc Switches_LEDs.ngd

Command Line: /zs/progs/xilinx/14.7/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
-filter iseconfig/filter.filter -intstyle ise -dd _ngo -nt timestamp -i -p
xc6slx9-tqg144-3 Switches_LEDs.ngc Switches_LEDs.ngd

Reading NGO file
"/zs/personal/projects/fpga/xilinx/Switches_LEDs/Switches_LEDs.ngc" ...
Gathering constraint information from source properties...
Done.

Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "Switches_LEDs.ngd" ...
Total REAL time to NGDBUILD completion:  3 sec
Total CPU time to NGDBUILD completion:   3 sec

Writing NGDBUILD log file "Switches_LEDs.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -filter "/zs/personal/projects/fpga/xilinx/Switches_LEDs/iseconfig/filter.filter" -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o Switches_LEDs_map.ncd Switches_LEDs.ngd Switches_LEDs.pcf
Using target part "6slx9tqg144-3".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 5 secs
Total CPU  time at the beginning of Placer: 5 secs

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:b) REAL time: 5 secs

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:b) REAL time: 5 secs

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:b) REAL time: 5 secs

Phase 4.2  Initial Placement for Architecture Specific Features

Phase 4.2  Initial Placement for Architecture Specific Features (Checksum:b) REAL time: 5 secs

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:b) REAL time: 5 secs

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:b) REAL time: 5 secs

Phase 7.3  Local Placement Optimization

Phase 7.3  Local Placement Optimization (Checksum:ccbfa83) REAL time: 5 secs

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:ccbfa83) REAL time: 5 secs

Phase 9.8  Global Placement
Phase 9.8  Global Placement (Checksum:ccbfa83) REAL time: 5 secs

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:ccbfa83) REAL time: 5 secs

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:ccbfa83) REAL time: 5 secs

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:ccbfa83) REAL time: 5 secs

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:ccbfa83) REAL time: 5 secs

Total REAL time to Placer completion: 5 secs
Total CPU  time to Placer completion: 5 secs
Running post-placement packing...
Writing output files...

Design Summary:
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                     0 out of  11,440    0%
  Number of Slice LUTs:                          0 out of   5,720    0%

Slice Logic Distribution:
  Number of occupied Slices:                     0 out of   1,430    0%
  Number of MUXCYs used:                         0 out of   2,860    0%
  Number of LUT Flip Flop pairs used:            0

IO Utilization:
  Number of bonded IOBs:                         4 out of     102    3%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       0 out of      16    0%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                1.00

Peak Memory Usage:  648 MB
Total REAL time to MAP completion:  6 secs
Total CPU time to MAP completion:   6 secs

Mapping completed.
See MAP report file "Switches_LEDs_map.mrp" for details.

Process "Map" completed successfully

Started : "Place & Route".
Running par...
Command Line: par -filter "/zs/personal/projects/fpga/xilinx/Switches_LEDs/iseconfig/filter.filter" -w -intstyle ise -ol high -mt off Switches_LEDs_map.ncd Switches_LEDs.ncd Switches_LEDs.pcf



Constraints file: Switches_LEDs.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment /zs/progs/xilinx/14.7/14.7/ISE_DS/ISE/.
   "Switches_LEDs" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.23 2013-10-13".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                     0 out of  11,440    0%
  Number of Slice LUTs:                          0 out of   5,720    0%

Slice Logic Distribution:
  Number of occupied Slices:                     0 out of   1,430    0%
  Number of MUXCYs used:                         0 out of   2,860    0%
  Number of LUT Flip Flop pairs used:            0

IO Utilization:
  Number of bonded IOBs:                         4 out of     102    3%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       0 out of      16    0%
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High
Router effort level (-rl):    High

Starting initial Timing Analysis.  REAL time: 4 secs
REAL time: 4 secs

Finished initial Timing Analysis.  Starting Router


Phase  1  : 2 unrouted;      REAL time: 4 secs

Phase  2  : 2 unrouted;      REAL time: 4 secs

Phase  3  : 0 unrouted;      REAL time: 4 secs

Phase  4  : 0 unrouted; (Par is working to improve performance)     REAL time: 4 secs

Updating file: Switches_LEDs.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 4 secs

     REAL time: 4 secs

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 4 secs

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 4 secs
Phase  6  : 0 unrouted; (Par is working to improve performance)
Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 4 secs

Phase 10  : 0 unrouted; (Par is working to improve performance)     REAL time: 4 secs
Total REAL time to Router completion: 4 secs
Total CPU time to Router completion: 4 secs

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)



Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs
Total CPU time to PAR completion: 4 secs

Peak Memory Usage:  599 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2

Writing design to file Switches_LEDs.ncd



PAR done!

Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".
Running trce...
Command Line: trce -filter /zs/personal/projects/fpga/xilinx/Switches_LEDs/iseconfig/filter.filter -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml Switches_LEDs.twx Switches_LEDs.ncd -o Switches_LEDs.twr Switches_LEDs.pcf
Loading device for application Rf_Device from file '6slx9.nph' in environment
/zs/progs/xilinx/14.7/14.7/ISE_DS/ISE/.
   "Switches_LEDs" is an NCD, version 3.2, device xc6slx9, package tqg144, speed
-3

Analysis completed Tue Sep 11 22:08:15 2018
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 3 secs

Process "Generate Post-Place & Route Static Timing" completed successfully

ok.

2018-09-11: vm4 - add license file

tingo@kg-vm4:~$ ll ~/.Xilinx/
total 12
drwxr-xr-x  2 tingo tingo 4096 Sep 11 21:47 ./
drwxr-xr-x 25 tingo tingo 4096 Sep 11 21:46 ../
-rw-r--r--  1 tingo tingo  984 Sep 11 21:47 Xilinx.lic

allow it to run as a script

tingo@kg-vm4:~$ chmod u+x ~/progs/xilinx/14.7/14.7/ISE_DS/run_ise.sh

ok.

2018-09-11: vm4 - start the installer (from a 'ssh -X ..' session)

tingo@kg-vm4:~/doc/Xilinx/temp/Xilinx_ISE_DS_Lin_14.7_1015_1$ ./xsetup

I select ISE WebPack, and

- use multiple cores for faster installation
- ensure Linux System Generator Symlinks

I give /home/tingo/progs/xilinx/14.7 as linstall dir, which results in /home/tingo/progs/xilinx/14.7/ISE_DS as install location

- deselect import tool preferences from previous version

and the installer starts. Finished

The environment variables are written to settings[32|64].(c)sh at "/home/tingo/progs/xilinx/14.7/14.7/ISE_DS". To launch the Xilinx tools, first source the settings script:

C-shell 64 bit environment...
source /home/tingo/progs/xilinx/14.7/14.7/ISE_DS/settings64.csh

Shell, Bash shell, Korn Shell 64 bit environment...
. /home/tingo/progs/xilinx/14.7/14.7/ISE_DS/settings64.sh

C-shell 32 bit environment...
source /home/tingo/progs/xilinx/14.7/14.7/ISE_DS/settings32.csh

Shell, Bash shell, Korn Shell 32 bit environment...
. /home/tingo/progs/xilinx/14.7/14.7/ISE_DS/settings32.sh

seems like something messed up, but ok. Create a start script.

tingo@kg-vm4:~$ cat ~/progs/xilinx/14.7/14.7/ISE_DS/run_ise.sh
#!/usr/bin/bash
. /home/tingo/progs/xilinx/14.7/ISE_DS/settings64.sh
ise

wrong. Fix it

#!/bin/bash
. /home/tingo/progs/xilinx/14.7/14.7/ISE_DS/settings64.sh
ise

ok.

2018-09-11: vm4 - check that the ncurses5 library is installed

tingo@kg-vm4:~$ sudo apt list --installed libncurses5
Listing... Done
libncurses5/stable,now 6.0+20161126-1+deb9u2 amd64 [installed]

ok.

2018-09-11: vm4 - install ISE on Debian. The machine runs Debian 9.5:

tingo@kg-vm4:~$ lsb_release -a
No LSB modules are available.
Distributor ID:    Debian
Description:    Debian GNU/Linux 9.5 (stretch)
Release:    9.5
Codename:    stretch

kernel

tingo@kg-vm4:~$ uname -a
Linux kg-vm4 4.9.0-8-amd64 #1 SMP Debian 4.9.110-3+deb9u4 (2018-08-21) x86_64 GNU/Linux

ok.