FPGA project - DE1 - CtrlModuleTutorial

Project: testing out CtrlModuleTutorial on the DE1 board

back to main Altera DE1 page.

History

2018-09-15: test - I compiled and uploaded the .svf file to the FPGA. F12 brings up the OSD. Reading a FAT16-formatted card works. Reading and loading (the needed files must be put on the SD card first) from a FAT32 formated card also works. Cool.

Fitter summary
Fitter Status : Successful - Sat Sep 15 20:08:13 2018
Quartus II 64-Bit Version : 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
Revision Name : CtrlModuleDemo
Top-level Entity Name : DE1_Toplevel
Family : Cyclone II
Device : EP2C20F484C7
Timing Models : Final
Total logic elements : 2,989 / 18,752 ( 16 % )
    Total combinational functions : 2,593 / 18,752 ( 14 % )
    Dedicated logic registers : 1,391 / 18,752 ( 7 % )
Total registers : 1391
Total pins : 283 / 315 ( 90 % )
Total virtual pins : 0
Total memory bits : 142,336 / 239,616 ( 59 % )
Embedded Multiplier 9-bit elements : 9 / 52 ( 17 % )
Total PLLs : 1 / 4 ( 25 % )

good to know.

2018-09-15: I cloned the repository for the CtrlModuleTutorial project. Changed Quartus II settings so I get generated files in a directory output_files, and so that it generates a .svf file.

FPGA project - DE1 - CtrlModuleTutorial

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