Xilinx Spartan-6 XC6SLX16 Core Board

name: Spartan-6 XC6SLX16 Core Board

  • FPGA: Xilinx Spartan 6 XC6SLX16-FTG256 - 14579 logic cells package: BGA 256 pins
  • non-volatile configuration device: W25Q64BV (previous version of the board had W25Q32BV?)
  • onboard 50 MHz oscillator
  • configuration: M25P80 spi flash chip, 1MB
  • RAM: 32 MB SDRAM, Micron MT48LC16M16A2
  • programming: JTAG interface
  • LEDS: 4
  • keys: 3 pushbuttons
  • power supply: 5V DC, 1A

J2 (JTAG header)

TMS
TDI
TDO
TCK
GND
3V3

clock

SYS_CLOCK - IO_L35P_CGLK17 - "LOC = A10"

LEDs

D4 - power LED (connected to 3V3)
D2 - FPGA_DONE
D1 - BANK2_IO_T9 - "LOC = T9"
D3 - BANK2_IO_r9 - "LOC = R9"

switches

SW2 - BANK2_IO_T8 - "LOC = T8"
SW3 - BANK2_IO_R7 - "LOC = R7"
SW1 - PROG_B -

Back to FPGA page.

Links

AliExpress Spartan6 development board XILINX FPGA SDRAM Spartan-6 core board XC6SLX16, DEC Emulation website,

tutorials

FPGA VGA Graphics in Verilog Part 1, part 2, part 3,

local links

DirtyJTAG, UrJTAG,

History

2021-08-04: I re-created this page on my self-hosted web server.

2018-12-20: I soldered pin headers to the board (U7 and U8).

2018-12-13: examples - pin definitions from examples Test01-led

//global system clock
NET "sys_clk"         LOC = A10     | IOSTANDARD = LVTTL;
//reset signal
NET "sys_rst_n"     LOC = R7     | IOSTANDARD = LVTTL;
//led_1 signal
NET "led_1"         LOC = T9     | IOSTANDARD = LVTTL;
//led_2 signal
NET "led_2"         LOC = R9     | IOSTANDARD = LVTTL;

Test02-keys

//global system clock
NET "sys_clk"         LOC = A10     | IOSTANDARD = LVTTL;
//reset signal
NET "sys_rst_n"     LOC = R7     | IOSTANDARD = LVTTL;
//led_1 signal
NET "led_1"         LOC = T9     | IOSTANDARD = LVTTL;
//led_2 signal
NET "led_2"         LOC = R9     | IOSTANDARD = LVTTL;
//key_1 signal
NET "key_1"         LOC = T8     | IOSTANDARD = LVTTL;

Test03-DCM

//global system clock
NET "CLK_50M_IN"         LOC = A10     | IOSTANDARD = LVTTL;
//reset signal
NET "sys_rst_n"         LOC = R7     | IOSTANDARD = LVTTL;
//33M
NET "CLK_33M_OUT"     LOC = T9     | IOSTANDARD = LVTTL;
//25M
NET "CLK_25M_OUT"     LOC = R9     | IOSTANDARD = LVTTL;

T9 is LED D1, R9 is LED D3.

2018-12-13: docs - the seller responded with a link to the documentation. It was on a chinese-only document site, but with the help of a colleague I got it downloaded. The documents are in chinese, but I can read the schematic and get the useful info from there.

2018-12-12: jtag test - I start urjtag and test

tingo@kg-bsbox:~$ jtag

UrJTAG 2018.09 #
Copyright (C) 2002, 2003 ETC s.r.o.
Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors

UrJTAG is free software, covered by the GNU General Public License, and you are
welcome to change it and/or distribute copies of it under certain conditions.
There is absolutely no warranty for UrJTAG.

warning: UrJTAG may damage your hardware!
Type "quit" to exit, "help" for help.

jtag> cable dirtyjtag
jtag> bsdl path /home/tingo/doc/Xilinx/docs/fpga/bsdl/
jtag> detect
IR length: 6
Chain length: 1
Device Id: 01000100000000000010000010010011 (0x44002093)
  Filename:     /home/tingo/doc/Xilinx/docs/fpga/bsdl//xc6slx16l_cpg196.bsd

looks good.

2018-12-12: power on test - I connected the board to power via the JTAG header to a Blue Pill with DirtyJTAG. LEDs D1 and D3 blinks, D2 and D4 is lit.

2018-12-12: docs - I asked the seller for download link to schematic and test code.

2018-12-06: package received, straight into my mailbox. The contents is just the FPGA board in an anti-static ziplock bag.

2018-11-14: the package has shipped.

2018-11-11: I ordered 1 x Spartan6 development board XILINX FPGA SDRAM Spartan-6 core board XC6SLX16, price was USD 17.10 with shipping included.