ao486 on C3 board

Project: ao486 on C3 board.

back to C3 board, main ao486 page.

local links

c1, e1, Altera Quartus II Fedora, FreeBSD,

History

2021-10-10: I re-created this page on my self-hosted web server.

2018-09-11: e1 - I changed the system.qsys file so it had the correct device, and ran qsys-generate again

[tingo@kg-elitebook soc]$ ~/progs/altera/13.1/quartus/sopc_builder/bin/qsys-generate --synthesis=VERILOG system.qsys
2018.09.11.18:44:38 Info: Saving generation log to /zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system_generation_1.rpt
2018.09.11.18:44:38 Info: Starting: <b>Create HDL design files for synthesis</b>
2018.09.11.18:44:38 Info: ip-generate --project-directory=/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/ --output-directory=/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=html:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system.html --report-file=sopcinfo:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system.sopcinfo --report-file=cmp:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system.cmp --report-file=qip:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system/synthesis/system.qip --report-file=svd --report-file=regmap:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system/synthesis/system.regmap --report-file=debuginfo:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system/synthesis/system.debuginfo --system-info=DEVICE_FAMILY="Cyclone III" --system-info=DEVICE=EP3C25Q240C8 --system-info=DEVICE_SPEEDGRADE=7 --component-file=/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system.qsys --language=VERILOG
2018.09.11.18:44:38 Info: Loading soc/system.qsys
2018.09.11.18:44:38 Info: Reading input file
2018.09.11.18:44:38 Info: Adding clk_sys [clock_source 14.0]
2018.09.11.18:44:38 Warning: clk_sys: Used clock_source <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module clk_sys
2018.09.11.18:44:38 Info: Adding ao486 [ao486 1.0]
2018.09.11.18:44:38 Warning: ao486: Component type <b>ao486</b> is not in the library
2018.09.11.18:44:38 Info: Parameterizing module ao486
2018.09.11.18:44:38 Info: Adding nios2 [altera_nios2_qsys 14.0]
2018.09.11.18:44:38 Warning: nios2: Used altera_nios2_qsys <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module nios2
2018.09.11.18:44:38 Info: Adding onchip_for_nios2 [altera_avalon_onchip_memory2 14.0]
2018.09.11.18:44:38 Warning: onchip_for_nios2: Used altera_avalon_onchip_memory2 <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module onchip_for_nios2
2018.09.11.18:44:38 Info: Adding jtag_uart [altera_avalon_jtag_uart 14.0]
2018.09.11.18:44:38 Warning: jtag_uart: Used altera_avalon_jtag_uart <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module jtag_uart
2018.09.11.18:44:38 Info: Adding pc_bus [pc_bus 1.0]
2018.09.11.18:44:38 Info: Parameterizing module pc_bus
2018.09.11.18:44:38 Info: Adding vga [vga 1.0]
2018.09.11.18:44:38 Info: Parameterizing module vga
2018.09.11.18:44:38 Info: Adding clk_vga [clock_source 14.0]
2018.09.11.18:44:38 Warning: clk_vga: Used clock_source <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module clk_vga
2018.09.11.18:44:38 Info: Adding sdram [altera_avalon_new_sdram_controller 14.0]
2018.09.11.18:44:38 Warning: sdram: Used altera_avalon_new_sdram_controller <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module sdram
2018.09.11.18:44:38 Info: Adding sound [sound 1.0]
2018.09.11.18:44:38 Info: Parameterizing module sound
2018.09.11.18:44:38 Info: Adding clk_sound [clock_source 14.0]
2018.09.11.18:44:38 Warning: clk_sound: Used clock_source <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module clk_sound
2018.09.11.18:44:38 Info: Adding rtc [rtc 1.0]
2018.09.11.18:44:38 Info: Parameterizing module rtc
2018.09.11.18:44:38 Info: Adding pit [pit 1.0]
2018.09.11.18:44:38 Info: Parameterizing module pit
2018.09.11.18:44:38 Info: Adding pic [pic 1.0]
2018.09.11.18:44:38 Warning: pic: Component type <b>pic</b> is not in the library
2018.09.11.18:44:38 Info: Parameterizing module pic
2018.09.11.18:44:38 Info: Adding hdd [hdd 1.0]
2018.09.11.18:44:38 Info: Parameterizing module hdd
2018.09.11.18:44:38 Info: Adding floppy [floppy 1.0]
2018.09.11.18:44:38 Info: Parameterizing module floppy
2018.09.11.18:44:38 Info: Adding pc_dma [pc_dma 1.0]
2018.09.11.18:44:38 Info: Parameterizing module pc_dma
2018.09.11.18:44:38 Info: Adding pio_input [altera_avalon_pio 14.0]
2018.09.11.18:44:38 Warning: pio_input: Used altera_avalon_pio <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module pio_input
2018.09.11.18:44:38 Info: Adding reset_only_ao486 [altera_reset_controller 14.0]
2018.09.11.18:44:38 Warning: reset_only_ao486: Used altera_reset_controller <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module reset_only_ao486
2018.09.11.18:44:38 Info: Adding pio_output [altera_avalon_pio 14.0]
2018.09.11.18:44:38 Warning: pio_output: Used altera_avalon_pio <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module pio_output
2018.09.11.18:44:38 Info: Adding reset_sys [altera_reset_controller 14.0]
2018.09.11.18:44:38 Warning: reset_sys: Used altera_reset_controller <b>13.1</b> (instead of 14.0)
2018.09.11.18:44:38 Info: Parameterizing module reset_sys
2018.09.11.18:44:38 Info: Adding driver_sound [driver_sound 1.0]
2018.09.11.18:44:38 Info: Parameterizing module driver_sound
2018.09.11.18:44:38 Info: Adding ps2 [ps2 1.0]
2018.09.11.18:44:38 Info: Parameterizing module ps2
2018.09.11.18:44:38 Info: Adding driver_sd [driver_sd 2.0]
2018.09.11.18:44:38 Warning: driver_sd: Component type <b>driver_sd</b> is not in the library
2018.09.11.18:44:38 Info: Parameterizing module driver_sd
2018.09.11.18:44:38 Info: Building connections
2018.09.11.18:44:38 Info: Parameterizing connections
2018.09.11.18:44:38 Info: Validating
2018.09.11.18:44:39 Info: Done reading input file
2018.09.11.18:44:39 Error: system.ao486: Component <b>ao486 1.0</b> not found or could not be instantiated
2018.09.11.18:44:39 Error: system.pic: Component <b>pic 1.0</b> not found or could not be instantiated
2018.09.11.18:44:39 Info: system.pio_input: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2018.09.11.18:44:39 Error: system.driver_sd: Component <b>driver_sd 2.0</b> not found or could not be instantiated
2018.09.11.18:44:41 Info: system: Generating <b>system</b> "<b>system</b>" for QUARTUS_SYNTH
2018.09.11.18:44:42 Info: pipeline_bridge_swap_transform: After transform: <b>24</b> modules, <b>101</b> connections
2018.09.11.18:44:42 Info: No custom instruction connections, skipping transform
2018.09.11.18:44:42 Error: null

still need to figure out how to get ao486, pic and driver_sd into the mix.

2018-09-11: e1 - I set up the ao486 project, just to see if I could get it to compile. I commented out all pin assignments, and all device info from the .qsf files. Opened the ./syn/soc/soc.qpf file in quartus II, and added corect FPGA device from the menu. Analysis and synthesis requires that qsys has ben run first. Qsys won't start from the menu, some Java error. So start it from the command line:

[tingo@kg-elitebook soc]$ pwd
/home/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc

run it

[tingo@kg-elitebook soc]$ ~/progs/altera/13.1/quartus/sopc_builder/bin/qsys-generate
2018.09.11.18:13:34 Error: You must specify a .qsys system to generate.

makes sense

[tingo@kg-elitebook soc]$ ~/progs/altera/13.1/quartus/sopc_builder/bin/qsys-generate --synthesis=VERILOG system.qsys
2018.09.11.18:15:11 Info: Saving generation log to /zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system_generation.rpt
2018.09.11.18:15:11 Info: Starting: <b>Create HDL design files for synthesis</b>
2018.09.11.18:15:11 Info: ip-generate --project-directory=/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/ --output-directory=/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system/synthesis/ --file-set=QUARTUS_SYNTH --report-file=html:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system.html --report-file=sopcinfo:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system.sopcinfo --report-file=cmp:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system.cmp --report-file=qip:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system/synthesis/system.qip --report-file=svd --report-file=regmap:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system/synthesis/system.regmap --report-file=debuginfo:/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system/synthesis/system.debuginfo --system-info=DEVICE_FAMILY="Cyclone IV E" --system-info=DEVICE=EP4CE115F29C7 --system-info=DEVICE_SPEEDGRADE=7 --component-file=/zs/tingo/personal/projects/fpga/Altera/c3/ao486/syn/soc/system.qsys --language=VERILOG
2018.09.11.18:15:11 Info: Loading soc/system.qsys
2018.09.11.18:15:11 Info: Reading input file
2018.09.11.18:15:11 Info: Adding clk_sys [clock_source 14.0]
2018.09.11.18:15:11 Warning: clk_sys: Used clock_source <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module clk_sys
2018.09.11.18:15:11 Info: Adding ao486 [ao486 1.0]
2018.09.11.18:15:11 Warning: ao486: Component type <b>ao486</b> is not in the library
2018.09.11.18:15:11 Info: Parameterizing module ao486
2018.09.11.18:15:11 Info: Adding nios2 [altera_nios2_qsys 14.0]
2018.09.11.18:15:11 Warning: nios2: Used altera_nios2_qsys <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module nios2
2018.09.11.18:15:11 Info: Adding onchip_for_nios2 [altera_avalon_onchip_memory2 14.0]
2018.09.11.18:15:11 Warning: onchip_for_nios2: Used altera_avalon_onchip_memory2 <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module onchip_for_nios2
2018.09.11.18:15:11 Info: Adding jtag_uart [altera_avalon_jtag_uart 14.0]
2018.09.11.18:15:11 Warning: jtag_uart: Used altera_avalon_jtag_uart <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module jtag_uart
2018.09.11.18:15:11 Info: Adding pc_bus [pc_bus 1.0]
2018.09.11.18:15:11 Info: Parameterizing module pc_bus
2018.09.11.18:15:11 Info: Adding vga [vga 1.0]
2018.09.11.18:15:11 Info: Parameterizing module vga
2018.09.11.18:15:11 Info: Adding clk_vga [clock_source 14.0]
2018.09.11.18:15:11 Warning: clk_vga: Used clock_source <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module clk_vga
2018.09.11.18:15:11 Info: Adding sdram [altera_avalon_new_sdram_controller 14.0]
2018.09.11.18:15:11 Warning: sdram: Used altera_avalon_new_sdram_controller <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module sdram
2018.09.11.18:15:11 Info: Adding sound [sound 1.0]
2018.09.11.18:15:11 Info: Parameterizing module sound
2018.09.11.18:15:11 Info: Adding clk_sound [clock_source 14.0]
2018.09.11.18:15:11 Warning: clk_sound: Used clock_source <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module clk_sound
2018.09.11.18:15:11 Info: Adding rtc [rtc 1.0]
2018.09.11.18:15:11 Info: Parameterizing module rtc
2018.09.11.18:15:11 Info: Adding pit [pit 1.0]
2018.09.11.18:15:11 Info: Parameterizing module pit
2018.09.11.18:15:11 Info: Adding pic [pic 1.0]
2018.09.11.18:15:11 Warning: pic: Component type <b>pic</b> is not in the library
2018.09.11.18:15:11 Info: Parameterizing module pic
2018.09.11.18:15:11 Info: Adding hdd [hdd 1.0]
2018.09.11.18:15:11 Info: Parameterizing module hdd
2018.09.11.18:15:11 Info: Adding floppy [floppy 1.0]
2018.09.11.18:15:11 Info: Parameterizing module floppy
2018.09.11.18:15:11 Info: Adding pc_dma [pc_dma 1.0]
2018.09.11.18:15:11 Info: Parameterizing module pc_dma
2018.09.11.18:15:11 Info: Adding pio_input [altera_avalon_pio 14.0]
2018.09.11.18:15:11 Warning: pio_input: Used altera_avalon_pio <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module pio_input
2018.09.11.18:15:11 Info: Adding reset_only_ao486 [altera_reset_controller 14.0]
2018.09.11.18:15:11 Warning: reset_only_ao486: Used altera_reset_controller <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module reset_only_ao486
2018.09.11.18:15:11 Info: Adding pio_output [altera_avalon_pio 14.0]
2018.09.11.18:15:11 Warning: pio_output: Used altera_avalon_pio <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module pio_output
2018.09.11.18:15:11 Info: Adding reset_sys [altera_reset_controller 14.0]
2018.09.11.18:15:11 Warning: reset_sys: Used altera_reset_controller <b>13.1</b> (instead of 14.0)
2018.09.11.18:15:11 Info: Parameterizing module reset_sys
2018.09.11.18:15:11 Info: Adding driver_sound [driver_sound 1.0]
2018.09.11.18:15:11 Info: Parameterizing module driver_sound
2018.09.11.18:15:11 Info: Adding ps2 [ps2 1.0]
2018.09.11.18:15:11 Info: Parameterizing module ps2
2018.09.11.18:15:11 Info: Adding driver_sd [driver_sd 2.0]
2018.09.11.18:15:11 Warning: driver_sd: Component type <b>driver_sd</b> is not in the library
2018.09.11.18:15:11 Info: Parameterizing module driver_sd
2018.09.11.18:15:11 Info: Building connections
2018.09.11.18:15:11 Info: Parameterizing connections
2018.09.11.18:15:11 Info: Validating
2018.09.11.18:15:12 Info: Done reading input file
2018.09.11.18:15:12 Error: system.ao486: Component <b>ao486 1.0</b> not found or could not be instantiated
2018.09.11.18:15:12 Error: system.pic: Component <b>pic 1.0</b> not found or could not be instantiated
2018.09.11.18:15:12 Info: system.pio_input: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
2018.09.11.18:15:12 Error: system.driver_sd: Component <b>driver_sd 2.0</b> not found or could not be instantiated
2018.09.11.18:15:15 Info: system: Generating <b>system</b> "<b>system</b>" for QUARTUS_SYNTH
2018.09.11.18:15:15 Info: pipeline_bridge_swap_transform: After transform: <b>24</b> modules, <b>101</b> connections
2018.09.11.18:15:15 Info: No custom instruction connections, skipping transform
2018.09.11.18:15:15 Error: null

hmm, needs more work. qsys-generate help

[tingo@kg-elitebook soc]$ ~/progs/altera/13.1/quartus/sopc_builder/bin/qsys-generate --help

Usage: qsys-generate <file>

   OPTION                                                 DESCRIPTION
   <1st arg file>                                         .qsys file
   -syn, --synthesis[=<VERILOG|VHDL>]                   ? Create synthesis files.
   -bsf, --block-symbol-file                            ? Create block symbol file (.bsf).
   -sim, --simulation=<VERILOG|VHDL>                    ? Create simulation model.
   -tb, --testbench=<SIMPLE|STANDARD>                   ? Create testbench system.
   -tb-sim, --testbench-simulation=<VERILOG|VHDL>       ? Create simulation model for the testbench system.
   -od, --output-directory=<value>                      ? The output directory
   -sp, --search-path=<value>                           ? IP component search path
   --family=<value>                                     ? The device family
   --part=<value>                                       ? The device part
   -amls, --allow-mixed-language-simulation             ? Enables mixed-language simulation model generation.
   -amltbs, --allow-mixed-language-testbench-simulation ? Enables mixed-language simulation testbench model generation.
   --jvm-max-heap-size=<value>                          ? Set the maximum heap memory size to be used
   -h, --help                                           ? Show help

QSYS-GENERATE
-------------
Generate a Qsys system.

<1st arg file>
     Required. The name of the .qsys system file to generate.

--synthesis[=<VERILOG|VHDL>]
     Optional. Create synthesis HDL files, used to compile the system in
     a Quartus II project.

--block-symbol-file
     Optional. Create a block symbol file (.bsf) for the system.

--simulation=<VERILOG|VHDL>
     Optional. Create a simulation model for the system. The simulation
     model contains generated HDL files for the simulator, and may
     include simulation-only features. The preferred simulation language
     must be specified.

--testbench=<SIMPLE|STANDARD>
     Optional. Create a testbench system. The testbench system
     instantiates the original system, adding bus functional models to
     drive the top-level interfaces. Once generated, the bus functional
     models can interact with the system in the simulator.

--testbench-simulation=<VERILOG|VHDL>
     Optional. After creating the testbench system, also create a
     simulation model for the testbench system.

--output-directory=<value>
     Optional. Set the output directory. Each generation target is
     created in a subdirectory of the output directory. If the output
     directory is not specified, a subdirectory of the current working
     directory matching the name of the system will be used.

--search-path=<value>
     Optional. If omitted, a standard default path will be used. If
     provided, a comma-separated list of paths will be searched. To
     include the standard path in your replacement, use "$", like
     "/extra/dir,$".

--family=<value>
     Optional. Set the device family.

--part=<value>
     Optional. Set the device part number. If set, this option overrides
     the "--family" option.

--allow-mixed-language-simulation
     Optional. When the value of this switch is true, if the author of a
     component in the design has declared a 'preferred' simulation
     language, a fileset of the component that best matches the language
     will be used for the simulation model generation. When this switch
     is not used (default) or its value is false, the simulation target
     language specified through the file-set switch will used for all
     components for simulation model generation.

--allow-mixed-language-testbench-simulation
     Optional. When the value of this switch is true, if the author of a
     component in the design has declared a 'preferred' simulation
     language, a fileset of the component that best matches the language
     will be used for the testbench simulation model generation. When
     this switch is not used (default) or its value is false, the
     simulation target language specified through the file-set switch
     will used for all components for testbench simulation model
     generation.

--jvm-max-heap-size=<value>
     Optional. The maximum memory size to be used for allocations when
     running this tool. This value is specified as <size><unit> where
     unit can be m (or M) for multiples of megabytes or g (or G) for
     multiples of gigabytes. The default value is 512m.

--help
     Optional. Display help for this tool

ok.