Altera Cyclone III EP3C25 board
Altera Cyclone III EP3C25 board aka "C3 board".
FPGA: Altera Cyclone III EP3C25Q240 (EP3C25Q240C8N)
the EP3C25 has - Logic elements (LE): 24624 - M9K embedded memory blocks: 66 (9216 bits per block, including parity bits) - embedded memory: 594 kbits - 18-bit x 18-bit embedded multipliers: 66 - phase-locked loops (PLL): 4 - maximum user I/O pins: 215 - differential channels: 83
- Q240 = 240-pin PQFP - it has 148 I/O
- oscillator: 50 MHz (pin 152 - clk)
- LEDs: power LED, running indicator LED
- power: 5V DC (center positive) barrel connector , onboard LDO regulator
- RAM: 2 x 16Mbyte / 8bit SDRAM (U4 - Hynix HY57V28820HCT-H, U6 - Hynix HY57V28820ETP-H) both are 4Banks x 4M x 8 bits
- flash memory (configuration): EPCS16 (U7)
- switches: S1 - Reset, connected to pin 181 (active low)
- LEDs: D1 - green, connected to PIN 233 (active low)
- D2 - power, red
connectors
JTAG - 5x2 header (J7) - key on left side
TCK_JTAG 1 2 GND TDO_JTAG 3 4 VDD33 TMS_JTAG 5 6 (nc) (nc) 7 8 (nc) TDI_JTAG 9 10 GND note: pin 5 (TMS) and 9 (TDI) have 10k pullups to VDD33. note: pin 1 (TCK) have 10k pulldown to GND. note: there are protection diodes (BAT54S) on JTAG signal lines (TDI, TCK, TDO, TMS)
AS - 5x2 header (J6) headers
Back to FPGA page.
Links
cores: minimig-mist, files: C3_VGABoard.zip,
Altera docs: Configuration Devices, Individual Computers wiki: Chamelon, github minimig-c3, minimig-firmware, minimig_firmware (2), minimig.net, MIST, retroramblings.net: Trials, Tribulations and Toolchains, custom VGA output board, DB9s and matrix board, latching power circuit, TG68 experiments, TurboChamelon64: menu controller code, menu controller code (2), Grant's MultiComp, Hamsterworks: FPGA projects - Simple SDRAM Controller, Github robinsonb5/TG68_MiniSOC, vasm, urjtag, ixo-jtag, OpenOCD, DirtyJTAG, STM32 Blue Pill ARM development board first look: from Arduino to bare metal programming, DEC Emulation website, possible projects: 8080 Minicomputer in FPGA,
local links
c1, GoodFET42, FT2232H breakout board,
local projects
abc80 on c3, ao486 on c3, Apple-One on c3, fpga-vt on c3, minimig on c3, multicomp on c3,
History / work log
2021-10-03: I re-created this page on my self-hosted web server.
2020-11-04: c1 - ada2p4 - testing, in the ../C3/abc80 project, in abc80.v, in the display video instatianton, I set .testpattern ( 0 ),
(it was .testpattern ( sw[5] ) originally) and I get a test text in colors. The colors are wrong (as in the text "BLUE" is actually yellow,
"GREEN" is purple, "PURPLE" is GREEN, "YELLOW" is blue, and so on. Other than that, the picture is perfect.
2020-11-04: C3 Board - current pin assignments, J3 & J4 J3
5V 1 2 3.3V U6_sdram_addr[0] 113 114 U6_sdram_addr[10]) U4_sdram_clk 117 118 U6_sdram_addr[1] U6_sdram_addr[2] 119 120 U6_sdram_addr[3] U6_sdram_ba[1] 126 127 U6_sdram_ba[0] U6_sdram_cs_n 128 131 U6_sdram_ras_n U6_sdram_cas_n 132 133 U6_sdram_we_n U6_sdram_addr[6] 134 135 leds[0] - green U6_sdram_addr[7] 137 139 U6_sdram_addr[8] U6_sdram_addr[11] 142 143 U6_sdram_cke U6_sdram_addr[9] 144 145 U6_sdram_dqm U6_sdram_data[3] 146 147 U6_sdram_data[2] U6_sdram_addr[5] 148 159 U6_sdram_data[1] U6_sdram_data[4] 160 161 U6_sdram_addr[4] U6_sdram_data[5] 162 164 U6_sdram_data[6] U6_sdram_data[7] 166 167 leds[1] - yellow U6_sdram_data[0] 168 169 leds[2] - orange 171 173 leds[3] - red (VCCint) 174 186 U6_sdram_clk GND 39 40 GND
J4
5V 1 2 3.3V U4_sdram_addr[3] 63 64 U4_sdram_addr[2] U4_sdram_addr[1] 65 68 U4_sdram_addr[0] U4_sdram_addr[10] 69 70 U4_sdram_ba[1] U4_sdram_ba[0] 71 72 U4_sdram_cs_n U4_sdram_ras_n 73 76 U4_sdram_cas_n U4_sdram_addr[6] 78 80 U4_sdram_addr[7] U4_sdram_addr[8] 81 82 U4_sdram_addr[9] U4_sdram_addr[11] 83 84 U4_sdram_cke (VCCint) 85 86 (GND) U4_sdram_dqm 87 88 U4_sdram_we_n U4_sdram_data[4] 93 94 95 98 U4_sdram_addr[5] 99 100 U4_sdram_data[3] (VCCint) 101 102 (GND) U4_sdram_data[6] 103 106 U4_sdram_data[2] U4_sdram_data[1] 107 108 U4_sdram_data[0] U4_sdram_data[7] 109 110 U4_sdram_addr[4] U4_sdram_data[5] 111 112 GND 39 40 GND
note: the leds are common anode (via a single 130 ohm resistor), so they need to be multiplexed to keep the current at acceptable levels.
2020-11-03: c1 - ada2p4 - testing, both the ../C3/abc80 and ../C3/abc80-de1 projects generate a moire / square pixels display on the VGA monitor (test pattern?), monitor reports 640 x 480 @ 60 Hz.
2020-11-03: c1 - ada2p4 - using a DirtyJTAG (Blue Pill) cable works:
tingo@kg-core1$ ~/work/urjtag/urjtag-2018.06/src/apps/jtag/jtag UrJTAG 2018.06 # Copyright (C) 2002, 2003 ETC s.r.o. Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors UrJTAG is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for UrJTAG. warning: UrJTAG may damage your hardware! Type "quit" to exit, "help" for help. jtag> cable dirtyjtag jtag> bsdl path /home/tingo/doc/Altera/docs/fpga/bsdl/ jtag> detect IR length: 10 Chain length: 1 Device Id: 00000010000011110011000011011101 (0x020F30DD) Filename: /home/tingo/doc/Altera/docs/fpga/bsdl//EP3C25Q240.BSD
good. Does 'cable probe' work?
jtag> cable probe Found USB cable: Flyswatter Connected to libftdi driver. jtag> detect Segmentation fault (core dumped)
no, it does not.
2020-11-03: c1 - ada2p4 - I reconnected a few loose wires, connected up the C3 board again, powered with a 5V DC (center positive), and connected up the FT2232 board, the board is detected
root@kg-core1# usbconfig -d ugen3.5 ugen3.5: <FTDI Dual RS232-HS> at usbus3, cfg=0 md=HOST spd=HIGH (480Mbps) pwr=ON (500mA)
the necessary files are created
root@kg-core1# sysctl dev.uftdi.0.ttyname; sysctl dev.uftdi.1.ttyname dev.uftdi.0.ttyname: U0 dev.uftdi.1.ttyname: U1 root@kg-core1# ls -l /dev/cuaU[01] crw-rw---- 1 uucp operator 0x2c8 Nov 3 22:18 /dev/cuaU0 crw-rw---- 1 uucp operator 0x2cf Nov 3 22:18 /dev/cuaU1 root@kg-core1# ls -l /dev/ttyU[01] crw-rw---- 1 root operator 0x2c5 Nov 3 22:18 /dev/ttyU0 crw-rw---- 1 root operator 0x2cb Nov 3 22:18 /dev/ttyU1 root@kg-core1# ls -l /dev/ugen3.5 lrw-rw---- 1 root cups 9 Nov 3 22:18 /dev/ugen3.5 -> usb/3.5.0 root@kg-core1# ls -l /dev/usb/3.5.0 crw-rw---- 1 root cups 0x2be Nov 3 22:18 /dev/usb/3.5.0
and my user is a member of the necessary groups:
root@kg-core1# groups tingo tingo wheel operator video dialer cups
still, I get a core dump when I try detect
tingo@kg-core1$ jtag UrJTAG 2019.12 # Copyright (C) 2002, 2003 ETC s.r.o. Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors UrJTAG is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for UrJTAG. warning: UrJTAG may damage your hardware! Type "quit" to exit, "help" for help. jtag> cable ft2232 vid=0x0403 pid=0x6010 Connected to libftdi driver. jtag> detect Segmentation fault (core dumped)
trying with the other version
tingo@kg-core1$ ~/work/urjtag/urjtag-2018.06/src/apps/jtag/jtag UrJTAG 2018.06 # Copyright (C) 2002, 2003 ETC s.r.o. Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors UrJTAG is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for UrJTAG. warning: UrJTAG may damage your hardware! Type "quit" to exit, "help" for help. jtag> cable ft2232 vid=0x0403 pid=0x6010 Connected to libftdi driver. jtag> detect Segmentation fault (core dumped)
not funny.
2018-11-02: I bought some VGA (female) to JST (or JST-like) 12-pins connector (female) on eBay a while ago Pinout is like this
VGA JST (DE15) (one row, 12 pins) 1 Red - 8 2 Green - 6 3 Blue - 4 4 5 GND (HSync) - 3 6 GND (Red) - 12 7 GND (Green) - 9 8 GND (Blue) - 7 9 10 GND (VSync, DDC) - 5 11 12 ID!/SDA - 2 13 HSync - 10 14 VSync - 11 15 ID3/SCL - 1
when the JST-like connector is facing you with the red-striped wire to the left. Unfortunately, the pin spacing on the JST-like connector is a bit smaller than the n(normal) 2.54mm, which is a shame. Don't know if I can bend pin headers to fit.
2018-10-05: adapter - PS/2 - I added another PS/2 socket to my adapter, now I can have both mouse and keyboard attached.
2018-09-14: C3 Board - I soldered pin headers to the free pins on J3 and J4 (plus GND, 3V3 and 5V) J3
135 leds[0] - green 167 leds[1] - yellow 169 leds[2] - orange 171 173 leds[3] - red
note: the leds are common anode (via a single 130 ohm resistor), so they need to be multiplexed to keep the current at acceptable levels
J4
94 95 98 112
currently unassigned.
2018-09-10: C3 Board - current pin assignments, updated J1
5V 1 2 3.3V
driveLED 233 234 (233: LED, 234: )
235 236
237 238
239 240
4 5
6 9
12 13
14 18
(19:VCCint) 19 ext_clk
(20: GND) 20 21
videoR0 22 37
videoR1 38 39 ps2Data
videoG0 41 43 ps2Clk
videoG1 44 45 sdSCLK
videoB0 46 49 sdCS
videoB1 50 51 sdMOSI
hSync 52 53 (53: VCCint)
vSync 56 57 sdMISO
GND 39 40 GND
and J2
5V 1 2 3.3V
(175: gnd) 175 176 sramAddress[9] (A9)
sramAddress[15] (A15) 177 181 n_reset (177: , 181: reset_n - reset switch active low)
n_sRamWE (WE#) 182 183 sramAddress[11] (A11)
sramAddress[13] (A13) 184 185 n_sRamOE (OE#)
sramAddress[8] (A8) 187 188 sramAddress[10] (A10)
sramAddress[14] (A14) 189 194 n_sRamCS (CE#)
sramAddress[12] (A12) 195 196 sramData[7] (DQ7)
sramAddress[7] (A7) 197 198 (198: VCCint)
(199: gnd) 199 200 sramAddress[6] (A6)
sramAddress[5] (A5) 201 202 sramData[6] (DQ6)
sramAddress[4] (A4) 203 207 sramData[5] (DQ5)
sramAddress[3] (A3) 214 216 sramData[4] (DQ4)
sramAddress[2] (A2) 217 218 sramData[3] (DQ3)
sramAddress[1] (A1) 219 220 (220: VCCint)
sramAddress[0] (A0) 221 222 (222: gnd)
sramData[0] (DQ0) 223 224 rxd1
sramData[1] (DQ1) 226 230 rts1
sramData[2] (DQ2) 231 232 txd1
GND 39 40 GND
that's all.
2018-09-06: adapter PS/2 - assign pins I connect GND and + 3V3 on the SD board
pin signal 39 ps2Data 43 ps2Clk
and wired up the adapter to the C3 board.
2018-09-06: adapter VGA - assign pins
pin signal 22 videoR0 38 videoR1 41 videoG0 44 videoG1 46 videoB0 50 videoB1 52 hSync 56 vSync 39 GND
and wired up the adapter to the C3 board.
2018-08-29: adapter - PS/2 - I also soldered 10k resistors to a PS/2 adapter that I had, as described on Grant's multicomp page. pins
+ 5V GND dat - ps2Data clk - ps2Clk
2018-08-29: adapter - VGA - soldered up a 2-bit VGA adapter as described on Grant's multicomp page. pins
red 0 - videoR0 red 1 - videoR1 green 0 - videoG0 green 1 - videoG1 blue 0 - videoB0 blue 1 - videoB1 hsync - hSync vsync - vSync GND
2018-08-28: I bought a couple of female VGA connectors at Kjell, so I can solder me some VGA adapters for the FPGA projects. Price was NOK 29.90 each.
2018-08-24: I built another RAM adapter, this time with pins on the breadboard, so I can use uncut dupont wires. I moved the RAM chip from the old adapter to this one. Yes - this adapter works.
2018-08-17: external SRAM - measured all connections with an ohmmeter - they are ok.
2018-08-16: C3 Board - current pin assignments J1
5V 1 2 3.3V
driveLED 233 234 (233: LED, 234: )
235 236
237 238
239 240
4 5
6 9
12 13
14 18
19 ext_clk
20 21
22 37
38 39
41 43
44 45 sdSCLK
46 49 sdCS
50 51 sdMOSI
52 53 (53: VCCint)
56 57 sdMISO
GND 39 40 GND
and J2
5V 1 2 3.3V
(175: gnd) 175 176 sramAddress[9] (A9)
sramAddress[15] (A15) 177 181 n_reset (177: , 181: reset_n - reset switch active low)
n_sRamWE (WE#) 182 183 sramAddress[11] (A11)
sramAddress[13] (A13) 184 185 n_sRamOE (OE#)
sramAddress[8] (A8) 187 188 sramAddress[10] (A10)
sramAddress[14] (A14) 189 194 n_sRamCS (CE#)
sramAddress[12] (A12) 195 196 sramData[7] (DQ7)
sramAddress[7] (A7) 197 198 (198: VCCint)
(199: gnd) 199 200 sramAddress[6] (A6)
sramAddress[5] (A5) 201 202 sramData[6] (DQ6)
sramAddress[4] (A4) 203 207 sramData[5] (DQ5)
sramAddress[3] (A3) 214 216 sramData[4] (DQ4)
sramAddress[2] (A2) 217 218 sramData[3] (DQ3)
sramAddress[1] (A1) 219 220 (220: VCCint)
sramAddress[0] (A0) 221 222 (222: gnd)
sramData[0] (DQ0) 223 224 rxd1
sramData[1] (DQ1) 226 230 rts1
sramData[2] (DQ2) 231 232 txd1
GND 39 40 GND
that's all.
2018-08-15: C3 Board - I tested with a SD card adapter too, but still no dice - it doesn't work.
2018-08-15: C3 Board - microSD card adapter, connections to J1
GND, + 3V3 45 sdSCLK 49 sdCS 51 sdMOSI 57 sdMISO
ok. (53 is VCCint, so that can't be used)
233 driveLED
let's see if that works. pinout of the microSD card adapter itself is (seen from the bottom)
3V3 CS MOSI CLK MISO GND
it has 10k resistors on the drive lines.
2018-08-10: C3 Board - external SRAM - corrected connections (J2) pins are
2 3V3
176 A15
177 A6
182 OE#
184 DQ4
187 DQ3
189 A14 183 WE#
195 A12 185 A13
197 A7 188 A8
194 A9
201 A5 196 A11
203 A4 198
214 A3 200 A10
217 A2 202 CE#
219 A1 207 DQ7
221 A0 216 DQ6
223 DQ0 218 DQ5
226 DQ1
231 DQ2
39 GND
that's it
2018-08-10: C3 Board - external SRAM - connections. I connected the SRAM to J2 as well. Pin assignments. pins are
2 3V3
176 A15
189 A14 183 WE#
195 A12 185 A13
197 A7 188 A8
199 A6 194 A9
201 A5 196 A11
203 A4 198 OE#
214 A3 200 A10
217 A2 202 CE#
219 A1 207 DQ7
221 A0 216 DQ6
223 DQ0 218 DQ5
226 DQ1 220 DQ4
231 DQ2 222 DQ3
39 GND
that's it Hmm, it seems that pin 198 and 220 are VCCINT, and pins 199 and 222 are GND, so I have to choose different pins for those
177 A6 182 OE# 184 DQ4 187 DQ3
done.
2018-08-10: C3 Board - external SRAM - I didn't have sockets, but I had some round headers at home, so today I soldered up a socket for the external SRAM. It has pin a couple of pin headers connected to ground (VSS, pin 16) so I can easily ground A16 (pin 2) but connecting its lead to a pin on the pin header.
2018-08-08: C3 Board - external memory, SRAM. I have several AS6C1008-55PCN, it is 128K x 8 bit, 55ns access time, single 2.7V - 5.5V power supply, "fully compatible with all Competitors 3.3V product", so this could be used. Hmm, I need a 32-pin socket.
2018-07-31: C3 Board - I soldered connectors (ok, pinheaders) to J1 and J2 on the board.
2018-07-30: C3 Board - connectors: with the power connector facing you, to the left of it we have J1, then (clockwise around the FPGA) J2, J3 and J4. J1
5V 1 2 3.3V 233 234 (233: LED, 234: ) 235 236 237 238 239 240 4 5 6 9 12 13 14 18 19 ext_clk 20 21 22 37 38 39 41 43 44 45 46 49 50 51 52 53 (53: VCCint) 56 57 GND 39 40 GND
J2
5V 1 2 3.3V 175 176 177 181 (177: , 181: reset_n - reset switch active low) 182 183 184 185 187 188 189 194 195 196 197 198 (198: VCCint) 199 200 (199: gnd) 201 202 203 207 214 216 217 218 219 220 (220: VCCint) 221 222 (222: gnd) 223 224 226 230 231 232 GND 39 40 GND
J3
5V 1 2 3.3V U6_sdram_addr[0] 113 114 U6_sdram_addr[10]) U4_sdram_clk 117 118 U6_sdram_addr[1] U6_sdram_addr[2] 119 120 U6_sdram_addr[3] U6_sdram_ba[1] 126 127 U6_sdram_ba[0] U6_sdram_cs_n 128 131 U6_sdram_ras_n U6_sdram_cas_n 132 133 U6_sdram_we_n U6_sdram_addr[6] 134 135 U6_sdram_addr[7] 137 139 U6_sdram_addr[8] U6_sdram_addr[11] 142 143 U6_sdram_cke U6_sdram_addr[9] 144 145 U6_sdram_dqm U6_sdram_data[3] 146 147 U6_sdram_data[2] U6_sdram_addr[5] 148 159 U6_sdram_data[1] U6_sdram_data[4] 160 161 U6_sdram_addr[4] U6_sdram_data[5] 162 164 U6_sdram_data[6] U6_sdram_data[7] 166 167 U6_sdram_data[0] 168 169 171 173 (VCCint) 174 186 U6_sdram_clk GND 39 40 GND
J4
5V 1 2 3.3V U4_sdram_addr[3] 63 64 U4_sdram_addr[2] U4_sdram_addr[1] 65 68 U4_sdram_addr[0] U4_sdram_addr[10] 69 70 U4_sdram_ba[1] U4_sdram_ba[0] 71 72 U4_sdram_cs_n U4_sdram_ras_n 73 76 U4_sdram_cas_n U4_sdram_addr[6] 78 80 U4_sdram_addr[7] U4_sdram_addr[8] 81 82 U4_sdram_addr[9] U4_sdram_addr[11] 83 84 U4_sdram_cke (VCCint) 85 86 (GND) U4_sdram_dqm 87 88 U4_sdram_we_n U4_sdram_data[4] 93 94 95 98 U4_sdram_addr[5] 99 100 U4_sdram_data[3] (VCCint) 101 102 (GND) U4_sdram_data[6] 103 106 U4_sdram_data[2] U4_sdram_data[1] 107 108 U4_sdram_data[0] U4_sdram_data[7] 109 110 U4_sdram_addr[4] U4_sdram_data[5] 111 112 GND 39 40 GND
so basically, J1 and J2 is were the free I/O pins are.
2018-07-27: c1 - let's see if I can program the Fampiga_C3.svf file via urjtag.
tingo@kg-core1$ pwd /home/tingo/personal/projects/fpga/altera/C3/minimig_c3/C3BoardProject tingo@kg-core1$ ll *svf -rw-r--r-- 1 tingo users - 1450388 Jul 27 22:23 Fampiga_C3.svf
set up urjtag
tingo@kg-core1$ jtag jtag> cable FT2232 vid=0403 pid=6010 Connected to libftdi driver. jtag> bsdl path /home/tingo/doc/Altera/docs/fpga/Cyclone_III/bsdl/ jtag> detect IR length: 10 Chain length: 1 Device Id: 00000010000011110011000011011101 (0x00000000020F30DD) Filename: /home/tingo/doc/Altera/docs/fpga/Cyclone_III/bsdl//EP3C25Q240.BSD
send the svf file
jtag> svf ./Fampiga_C3.svf
it does. Without external interfaces, I have no way of knowing if it worked. But at least it programmed.
2018-07-26: c1 - urjtag session
tingo@kg-core1$ pwd /usr/home/tingo/doc/Altera/CycloneIII_EP3C25 tingo@kg-core1$ jtag UrJTAG 0.10 #1502 Copyright (C) 2002, 2003 ETC s.r.o. Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors UrJTAG is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for UrJTAG. WARNING: UrJTAG may damage your hardware! Type "quit" to exit, "help" for help. jtag> cable FT2232 vid=0403 pid=6010 Connected to libftdi driver. jtag> bsdl path /home/tingo/doc/Altera/docs/fpga/Cyclone_III/bsdl/ jtag> detect IR length: 10 Chain length: 1 Device Id: 00000010000011110011000011011101 (0x00000000020F30DD) Filename: /home/tingo/doc/Altera/docs/fpga/Cyclone_III/bsdl//EP3C25Q240.BSD
other commands
jtag> print chain
No. Manufacturer Part Stepping Instruction Register
------------------------------------------------------------------------------------------------------------------
0 EP3C25Q240 BYPASS BYPASS
jtag> print instructions
Active Instruction Register
-------------------------------------------------------------
X BYPASS BYPASS
EXTEST BSR
SAMPLE/PRELOAD BSR
IDCODE DIR
USERCODE USERCODE
CLAMP BYPASS
HIGHZ BYPASS
CONFIG_IO IOCSR
try to download a svf
jtag> svf ./docs/samples/3C25/hello_led/hello_led.svf Warning svf: unimplemented mode 'ABSENT' for TRST
ok, change the svf file so that the line for TRST is commented out
jtag> svf ./svfs/hello_led.svf
and it worked. Now the C3 board blinks the "Hello world" LED demo.
2018-07-26: OpenOCD - corrected the config file
# Altera Cyclone III EP3C25 FPGA # Version Part Number Manuf. ID LSB # 0000 0010 0000 1111 0031 000 0110 1110 1 jtag newtap ep3c25 tap -ignore-version -expected-id 0x020f30dd -irlen 10
apparently, irlen is 10 for all Altera / Intel FPGAs and CPLDs. New test
tingo@kg-core1$ openocd -f ft2232h.cfg -f altera-ep3c25.cfg Open On-Chip Debugger 0.10.0 Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst adapter speed: 30000 kHz jtag Warn : libusb_detach_kernel_driver() failed with LIBUSB_ERROR_OTHER, trying to continue anyway Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling" Info : clock speed 30000 kHz Info : JTAG tap: ep3c25.tap tap/device found: 0x020f30dd (mfg: 0x06e (Altera), part: 0x20f3, ver: 0x0) Warn : gdb services need one or more targets defined
telnet connection
tingo@kg-core1$ telnet localhost 4444 Trying 127.0.0.1... Connected to localhost. Escape character is '^]'. Open On-Chip Debugger > scan_chain TapName Enabled IdCode Expected IrLen IrCap IrMask -- ------------------- -------- ---------- ---------- ----- ----- ------ 0 ep3c25.tap Y 0x020f30dd 0x*20f30dd 10 0x01 0x03
ok
2018-07-26: OpenOCD - test the config file
tingo@kg-core1$ openocd -f ft2232h.cfg -f altera-ep3c25.cfg Open On-Chip Debugger 0.10.0 Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst adapter speed: 30000 kHz jtag Warn : libusb_detach_kernel_driver() failed with LIBUSB_ERROR_OTHER, trying to continue anyway Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling" Info : clock speed 30000 kHz Info : JTAG tap: ep3c25.tap tap/device found: 0x020f30dd (mfg: 0x06e (Altera), part: 0x20f3, ver: 0x0) Error: IR capture error at bit 2, saw 0x05 not 0x...3 Warn : Bypassing JTAG setup events due to errors Warn : gdb services need one or more targets defined
telnet connection
tingo@kg-core1$ telnet localhost 4444 Trying 127.0.0.1... Connected to localhost. Escape character is '^]'. Open On-Chip Debugger > scan_chain TapName Enabled IdCode Expected IrLen IrCap IrMask -- ------------------- -------- ---------- ---------- ----- ----- ------ 0 ep3c25.tap Y 0x020f30dd 0x*20f30dd 2 0x01 0x03
ok.
2018-07-26: create a OpenOCD config file for the EP3C25:
tingo@kg-core1$ pwd /home/tingo/doc/Altera/CycloneIII_EP3C25 tingo@kg-core1$ cat altera-ep3c25.cfg # Altera Cyclone III EP3C25 FPGA # Version Part Number Manuf. ID LSB # 0000 0010 0000 1111 0031 000 0110 1110 1 jtag newtap ep3c25 tap -ignore-version -expected-id 0x020f30dd -irlen 2
ok
2018-07-26: JTAG test 2 - I powered the C3 board via the +5V power connector, connected JTAG pins + GND to FT2232H, now OpenOCD looks better:
tingo@kg-core1$ openocd -f ft2232h.cfg Open On-Chip Debugger 0.10.0 Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst adapter speed: 30000 kHz jtag Warn : libusb_detach_kernel_driver() failed with LIBUSB_ERROR_OTHER, trying to continue anyway Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling" Info : clock speed 30000 kHz Warn : There are no enabled taps. AUTO PROBING MIGHT NOT WORK!! Info : JTAG tap: auto0.tap tap/device found: 0x020f30dd (mfg: 0x06e (Altera), part: 0x20f3, ver: 0x0) Warn : AUTO auto0.tap - use "jtag newtap auto0 tap -irlen 2 -expected-id 0x020f30dd" Error: IR capture error at bit 2, saw 0x3FFFFFFFFFFFFD55 not 0x...3 Warn : Bypassing JTAG setup events due to errors Warn : gdb services need one or more targets defined
ok, and via telnet connection
tingo@kg-core1$ telnet localhost 4444 Trying 127.0.0.1... Connected to localhost. Escape character is '^]'. Open On-Chip Debugger > scan_chain TapName Enabled IdCode Expected IrLen IrCap IrMask -- ------------------- -------- ---------- ---------- ----- ----- ------ 0 auto0.tap Y 0x020f30dd 0x00000000 2 0x01 0x03
cool.
2018-07-26: JTAG test 1 - I connected up the C3 board to the first channel JTAG pins on the FT2232 breakout board, and to GND and 3.3V (to VDD33 on C3 board JTAG connector) and ran OpenOCD, like this
tingo@kg-core1$ openocd -f ft2232h.cfg Open On-Chip Debugger 0.10.0 Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst adapter speed: 30000 kHz jtag Warn : libusb_detach_kernel_driver() failed with LIBUSB_ERROR_OTHER, trying to continue anyway Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling" Info : clock speed 30000 kHz Warn : There are no enabled taps. AUTO PROBING MIGHT NOT WORK!! Error: JTAG scan chain interrogation failed: all ones Error: Check JTAG interface, timings, target power, etc. Error: Trying to use configured scan chain anyway... Warn : Bypassing JTAG setup events due to errors Warn : gdb services need one or more targets defined Info : accepting 'telnet' connection on tcp/4444 TapName Enabled IdCode Expected IrLen IrCap IrMask -- ------------------- -------- ---------- ---------- ----- ----- ------ shutdown command invoked Info : dropped 'telnet' connection
ok, it didn't like that.
2018-07-26: pin assignments on the board
pin signal description 152 clk 50 MHz oscillator input 181 reset_n reset switch input, active low 233 LED LED status indicator
U4 - the chip is 16MB (128 Mbit), 8bit wide data bus.
Row address: RA0 - RA11 Column address: CA0 - CA9 Auto-precharge flag: A10
U4 SDRAM signals
pin signal description 83 U4_sdram_addr[11] SDRAM address 69 U4_sdram_addr[10] 82 U4_sdram_addr[9] 81 U4_sdram_addr[8] 80 U4_sdram_addr[7] 78 U4_sdram_addr[6] 99 U4_sdram_addr[5] 110 U4_sdram_addr[4] 63 U4_sdram_addr[3] 64 U4_sdram_addr[2] 65 U4_sdram_addr[1] 68 U4_sdram_addr[0] 70 U4_sdram_ba[1] SDRAM bank address 71 U4_sdram_ba[0] 76 U4_sdram_cas_n 84 U4_sdram_cke 117 U4_sdram_clk 72 U4_sdram_cs_n 73 U4_sdram_ras_n 88 U4_sdram_we_n 87 U4_sdram_dqm 109 U4_sdram_data[7] SDRAM data bus 103 U4_sdram_data[6] 111 U4_sdram_data[5] 93 U4_sdram_data[4] 100 U4_sdram_data[3] 106 U4_sdram_data[2] 107 U4_sdram_data[1] 108 U4_sdram_data[0]
U6 - the chip is 16MB (128 Mbit), 8bit wide data bus.
Row address: RA0 - RA11 Column address: CA0 - CA9 Auto-precharge flag: A10
U6 SDRAM signals pin signal description
142 U6_sdram_addr[11] SDRAM address 114 U6_sdram_addr[10] 144 U6_sdram_addr[9] 139 U6_sdram_addr[8] 137 U6_sdram_addr[7] 134 U6_sdram_addr[6] 148 U6_sdram_addr[5] 161 U6_sdram_addr[4] 120 U6_sdram_addr[3] 119 U6_sdram_addr[2] 118 U6_sdram_addr[1] 113 U6_sdram_addr[0] 126 U6_sdram_ba[1] SDRAM bank address 127 U6_sdram_ba[0] 132 U6_sdram_cas_n 143 U6_sdram_cke 186 U6_sdram_clk 128 U6_sdram_cs_n 131 U6_sdram_ras_n 133 U6_sdram_we_n 145 U6_sdram_dqm 166 U6_sdram_data[7] SDRAM data bus 164 U6_sdram_data[6] 162 U6_sdram_data[5] 160 U6_sdram_data[4] 146 U6_sdram_data[3] 147 U6_sdram_data[2] 159 U6_sdram_data[1] 168 U6_sdram_data[0]
ok.
2018-07-25: power on test - I connected the C3 board to a 5V PSU (center positive). The power LED lights up red, the green LED (D1) fades in and out for a while (it runs Nios2 "pwm demo").
2018-07-25: AS pinout (J6) - connection to EPCS16?
DCLK_AS 1 2 GND CFG_DN_AS 3 4 VDD33 nCFG_AS 5 6 nCE_AS DATA_AS 7 8 nCS_AS ASDI_AS 9 10 GND
note:
2018-07-25: JTAG pinout (J7)
TCK_JTAG 1 2 GND TDO_JTAG 3 4 VDD33 TMS_JTAG 5 6 (nc) (nc) 7 8 (nc) TDI_JTAG 9 10 GND note: pin 5 (TMS) and 9 (TDI) have 10k pullups to VDD33. note: pin 1 (TCK) have 10k pulldown to GND. note: there are protection diodes (BAT54S) on JTAG signal lines (TDI, TCK, TDO, TMS)
2018-07-25: vj-uart - Virtual JTAG Uart for Altera devices. Looks interesting.
2018-07-15: programmer - got a notice that the USB Blaster was shipped, estimated delivery Tuesday July 31 - Thursday September 06.
2018-07-14: programmer - it looks like the only thing that can program Altera FPGAs (as opposed to use the JTAG interface for debugging) is an Altera USB Blaster or a clone. So I ordered 1 x Altera Mini Usb Blaster Cable For CPLD FPGA NIOS JTAG Altera Programmer NEW from a seller on ebay for USD 2.60, shipping included. It shoould be 1 x USB BLASTER Programmer, 1 x USB cable, 1 x 10-pin JTAG cable.
2018-07-13: I also have a GoodFET42 adapter, perhaps it could be used? Or even a STM32 Blue Pill or Black Pill board, with the right firmware.
2018-07-13: perhaps urjtag together with a suitable JTAG adapter (ixo-jtag?) can be used for programming Altera devices? It looks like OpenOCD also has support for Altera USB Blaster compatible adapters.
2018-07-11: perhaps Grant Searle's Multicomp could be ported to the C3 board? The RetroBrew Computers wiki have Multicomp designs for both CycloneII and CycloneIV boards. Sure, Building your own custom computer with the MiST FPGA board: part 1, part 2 (Github: wsoltys/multicomp) is for the MiST which has a CycloneIII.
2018-07-07: - the latest version of Quartus II that supports the Cyclone III family is Quartus II v13.1. Grabbing a copy of the free web edition now.
2015-09-08: the minimig-c3 project is a port of the Minimig core to a generic Cyclone III FPGA board.
2013-05-16: I picked up the package at my local post office (Sofienberg postkontor) today.
2013-05-04: I received a shipping notice.
2013-05-02: I bought the board, complete with 2 x SDRAM chips, bringing the total memory up to 32 Mbyte. Total price was USD 114.- shipping included.
2013-04-29: the seller responded, adding another SDRAM chip would cost me USD 5.- including testing. Good deal.
2013-04-27: I found a Cyclone III FPGA EP3C25 board on eBay and asked the seller how I could buy it with 2 SDRAM chips instead of one.