Xilinx ISE WebPACK - Fedora

Xilinx: ISE WebPACK

Links: ArchLinux: Xilinx ISE WebPACK, Embedded Micro Installing ISE, Scripting ISE using Tcl, Scripting an entire ISE flow,

local links: e1,

back to main ISE page.

History

2018-10-30: e1 - HelloWorld project -Implement Top Module, then Generate programming file. Next I launch iMPACT, and manually set it to generate a .svf file from the .bit file. That works.

2018-10-30: e1 - FPGAOric.xise contains

    <property xil_pn:name="Working Directory" xil_pn:value="build" xil_pn:valueState="non-default"/>

interesting.

2018-10-30: e1 - HelloWorld project - the HelloWorld.xise file contains this

    <property xil_pn:name="Working Directory" xil_pn:value="/home/tingo/personal/projects/fpga/Xilinx/helloWorld/HelloWorld" xil_pn:valueState="non-default"/>

ok. Clean up project files, close the project, change it to

    <property xil_pn:name="Working Directory" xil_pn:value="build" xil_pn:valueState="non-default"/>

and open the project again. Yes, that works, now ISE asks to create the "build" directory, and then the project use that. Good.

2018-08-22: e1 - testing ISE with this Hello World project. Write the Verilog and .ucf file, the double click on "Generate Programming File". After some minutes, I have three green checkmarks. output from the console window (not sure if ISE keeps text reports)

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "/zs/tingo/personal/projects/fpga/Xilinx/helloWorld/HelloWorld/HelloWorld.xst" -ofn "/zs/tingo/personal/projects/fpga/Xilinx/helloWorld/HelloWorld/HelloWorld.syr"
Reading design: HelloWorld.prj

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "/zs/tingo/personal/projects/fpga/Xilinx/helloWorld/HelloWorld/HelloWorld.v" into library work
Parsing module <HelloWorld>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <HelloWorld>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <HelloWorld>.
    Related source file is "/zs/tingo/personal/projects/fpga/Xilinx/helloWorld/HelloWorld/HelloWorld.v".
    Found 22-bit register for signal <freq_div>.
    Found 22-bit adder for signal <freq_div[21]_GND_1_o_add_1_OUT> created at line 29.
    Summary:
    inferred   1 Adder/Subtractor(s).
    inferred  22 D-type flip-flop(s).
Unit <HelloWorld> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 1
 22-bit adder                                          : 1
# Registers                                            : 1
 22-bit register                                       : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <HelloWorld>.
The following registers are absorbed into counter <freq_div>: 1 register on signal <freq_div>.
Unit <HelloWorld> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Counters                                             : 1
 22-bit up counter                                     : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <HelloWorld> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block HelloWorld, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 22
 Flip-Flops                                            : 22

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_in                             | BUFGP                  | 22    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 2.066ns (Maximum Frequency: 484.062MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 3.634ns
   Maximum combinational path delay: No path found

=========================================================================

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 HelloWorld.ngc HelloWorld.ngd

Command Line:
/zs/tingo/progs_lin/xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild
-intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 HelloWorld.ngc
HelloWorld.ngd

Reading NGO file
"/zs/tingo/personal/projects/fpga/Xilinx/helloWorld/HelloWorld/HelloWorld.ngc"
...
Gathering constraint information from source properties...
Done.

Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "HelloWorld.ngd" ...
Total REAL time to NGDBUILD completion:  4 sec
Total CPU time to NGDBUILD completion:   3 sec

Writing NGDBUILD log file "HelloWorld.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o HelloWorld_map.ncd HelloWorld.ngd HelloWorld.pcf
Using target part "6slx9tqg144-3".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 8 secs
Total CPU  time at the beginning of Placer: 5 secs

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:92f) REAL time: 10 secs

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:92f) REAL time: 10 secs

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:92f) REAL time: 10 secs

Phase 4.2  Initial Placement for Architecture Specific Features

Phase 4.2  Initial Placement for Architecture Specific Features
REAL time: 10 secs

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:791a0b53) REAL time: 10 secs

(Checksum:791a0b53) Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:791a0b53) REAL time: 10 secs

Phase 7.3  Local Placement Optimization

Phase 7.3  Local Placement Optimization (Checksum:36e05ac3) REAL time: 10 secs

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:36e05ac3) REAL time: 10 secs

Phase 9.8  Global Placement
...
...
Phase 9.8  Global Placement (Checksum:640fb5c8) REAL time: 11 secs

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:640fb5c8) REAL time: 11 secs

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:640fb5c8) REAL time: 11 secs

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:640fb5c8) REAL time: 11 secs

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:640fb5c8) REAL time: 11 secs

Total REAL time to Placer completion: 11 secs
Total CPU  time to Placer completion: 6 secs
Running post-placement packing...
Writing output files...

Design Summary:
Number of errors:      0
Number of warnings:    0
Slice Logic Utilization:
  Number of Slice Registers:                    22 out of  11,440    1%
    Number used as Flip Flops:                  22
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                         22 out of   5,720    1%
    Number used as logic:                       21 out of   5,720    1%
      Number using O6 output only:               0
      Number using O5 output only:              20
      Number using O5 and O6:                    1
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   1,440    0%
    Number used exclusively as route-thrus:      1
      Number with same-slice register load:      0
      Number with same-slice carry load:         1
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                     6 out of   1,430    1%
  Number of MUXCYs used:                        24 out of   2,860    1%
  Number of LUT Flip Flop pairs used:           22
    Number with an unused Flip Flop:             0 out of      22    0%
    Number with an unused LUT:                   0 out of      22    0%
    Number of fully used LUT-FF pairs:          22 out of      22  100%
    Number of unique control sets:               1
    Number of slice register sites lost
      to control set restrictions:               2 out of  11,440    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         2 out of     102    1%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
    Number used as BUFGs:                        1
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

Average Fanout of Non-Clock Nets:                1.04

Peak Memory Usage:  852 MB
Total REAL time to MAP completion:  11 secs
Total CPU time to MAP completion:   6 secs

Mapping completed.
See MAP report file "HelloWorld_map.mrp" for details.

Process "Map" completed successfully

Started : "Place & Route".
Running par...
Command Line: par -w -intstyle ise -ol high -mt off HelloWorld_map.ncd HelloWorld.ncd HelloWorld.pcf



Constraints file: HelloWorld.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment
/zs/tingo/progs_lin/xilinx/14.7/ISE_DS/ISE/.
   "HelloWorld" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRODUCTION 1.23 2013-10-13".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                    22 out of  11,440    1%
    Number used as Flip Flops:                  22
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                         22 out of   5,720    1%
    Number used as logic:                       21 out of   5,720    1%
      Number using O6 output only:               0
      Number using O5 output only:              20
      Number using O5 and O6:                    1
      Number used as ROM:                        0
    Number used as Memory:                       0 out of   1,440    0%
    Number used exclusively as route-thrus:      1
      Number with same-slice register load:      0
      Number with same-slice carry load:         1
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                     6 out of   1,430    1%
  Number of MUXCYs used:                        24 out of   2,860    1%
  Number of LUT Flip Flop pairs used:           22
    Number with an unused Flip Flop:             0 out of      22    0%
    Number with an unused LUT:                   0 out of      22    0%
    Number of fully used LUT-FF pairs:          22 out of      22  100%
    Number of slice register sites lost
      to control set restrictions:               0 out of  11,440    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         2 out of     102    1%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of      32    0%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       1 out of      16    6%
    Number used as BUFGs:                        1
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High
Router effort level (-rl):    High

Starting initial Timing Analysis.  REAL time: 3 secs
Finished initial Timing Analysis.  REAL time: 3 secs

Starting Router


Phase  1  : 56 unrouted;      REAL time: 4 secs

     REAL time: 4 secs
Phase  2  : 28 unrouted;
     REAL time: 4 secs
Phase  3  : 0 unrouted;
(Par is working to improve performance)     REAL time: 4 secs
Phase  4  : 0 unrouted;
Updating file: HelloWorld.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 5 secs

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 5 secs

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 5 secs

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 5 secs

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 5 secs

(Par is working to improve performance)     REAL time: 5 secs
Phase 10  : 0 unrouted; Total REAL time to Router completion: 5 secs
Total CPU time to Router completion: 4 secs

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing  
                                            |             |    Slack   | Achievable | Errors |    Score  
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP       |         N/A|     1.842ns|     N/A|           0
  _in_BUFGP                                 | HOLD        |     0.504ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
   constraint is not analyzed due to the following: No paths covered by this
   constraint; Other constraints intersect with this constraint; or This
   constraint was disabled by a Path Tracing Control. Please run the Timespec
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs
Total CPU time to PAR completion: 4 secs

Peak Memory Usage:  606 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2

Writing design to file HelloWorld.ncd



PAR done!

Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".
Running trce...
Command Line: trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml HelloWorld.twx HelloWorld.ncd -o HelloWorld.twr HelloWorld.pcf
Loading device for application Rf_Device from file '6slx9.nph' in environment
/zs/tingo/progs_lin/xilinx/14.7/ISE_DS/ISE/.
   "HelloWorld" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3

Analysis completed Wed Aug 22 16:07:09 2018
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 3 secs

Process "Generate Post-Place & Route Static Timing" completed successfully

Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f HelloWorld.ut HelloWorld.ncd

Process "Generate Programming File" completed successfully

large enough.

2018-07-24: e1 - space occupied

[tingo@kg-elitebook xilinx]$ pwd
/home/tingo/progs/xilinx
[tingo@kg-elitebook xilinx]$ du -sh 14.7
18G    14.7

yep, that's a lot.

2018-07-24: e1 - I created a script to start ISE

[tingo@kg-elitebook ~]$ l ~/progs/xilinx/14.7/ISE_DS/run_ise.sh
/home/tingo/progs/xilinx/14.7/ISE_DS/run_ise.sh*

contents

[tingo@kg-elitebook ~]$ cat ~/progs/xilinx/14.7/ISE_DS/run_ise.sh
#!/usr/bin/bash
. /home/tingo/progs/xilinx/14.7/ISE_DS/settings64.sh
ise

so test it. It works, and after setting up the license file is located at:

[tingo@kg-elitebook ~]$ pwd
/home/tingo
[tingo@kg-elitebook ~]$ ls -l .Xilinx/
total 4
-rw-rw-r--. 1 tingo tingo 984 Jul 24 21:51 Xilinx.lic

ok

2018-07-24: e1 - start the ISE installer

[tingo@kg-elitebook Xilinx_ISE_DS_Lin_14.7_1015_1]$ pwd
/zs/tingo/doc/Xilinx/ise_webpack/Xilinx_ISE_DS_Lin_14.7_1015_1
[tingo@kg-elitebook Xilinx_ISE_DS_Lin_14.7_1015_1]$ ./xsetup

(I selected the ISE WebPACK option) I also selected

- use multiple cores for installation
- acquire or manage a license key
- ensure linux system generator symlinks

I change install location to /home/tingo/progs/xilinx/14.7/ISE_DS and choose not to import tool preferences from previous versions options summary

Install Location(s):

/home/tingo/progs/xilinx/14.7/ISE_DS

Edition : ISE WebPACK

Option: Acquire or Manage a License Key

ISE DS Common

Install Location: /home/tingo/progs/xilinx/14.7/ISE_DS/common

Module: ISE DS Common

EDK

Install Location: /home/tingo/progs/xilinx/14.7/ISE_DS/EDK

Module: EDK

PlanAhead Analysis Tool

Install Location: /home/tingo/progs/xilinx/14.7/ISE_DS/PlanAhead

Module: PlanAhead Files

Option: setupEnv.sh

ISE

Install Location: /home/tingo/progs/xilinx/14.7/ISE_DS/ISE

Module: Design Environment Tools

Module: WebPACK Devices

Option: Install Linux System Generator Info XML

Option: Ensure Linux System Generator Symlinks

Option: Enable WebTalk to send software, IP and device usage statistics to Xilinx (Always enabled for WebPACK license) ok. After it says "install completed", and

The environment variables are written to settings[32|64].(c)sh at "/home/tingo/progs/xilinx/14.7/ISE_DS". To launch the Xilinx tools, first source the settings script:
C-shell 64 bit environment...
source /home/tingo/progs/xilinx/14.7/ISE_DS/settings64.csh
Shell, Bash shell, Korn Shell 64 bit environment...
. /home/tingo/progs/xilinx/14.7/ISE_DS/settings64.sh
C-shell 32 bit environment...
source /home/tingo/progs/xilinx/14.7/ISE_DS/settings32.csh
Shell, Bash shell, Korn Shell 32 bit environment...
. /home/tingo/progs/xilinx/14.7/ISE_DS/settings32.sh

nice to know.

2018-07-24: e1 - the ISE installer needs ncurses-compat-libs, so install that

[tingo@kg-elitebook ~]$ sudo dnf install ncurses-compat-libs
[..]
Total download size: 303 k
Installed size: 1.1 M
[..]
Installed:
  ncurses-compat-libs.x86_64 6.1-5.20180224.fc28                                                                                                                               

ok

2018-07-24: e1 - I'm using my Fedora laptop to install on.

[tingo@kg-elitebook ~]$ cat /etc/fedora-release
Fedora release 28 (Twenty Eight)
[tingo@kg-elitebook ~]$ uname -a
Linux kg-elitebook.kg4.no 4.17.5-200.fc28.x86_64 #1 SMP Tue Jul 10 13:39:04 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux

ok.