ABC80 on C3 board

Project: try to get abc80 running on a Cyclone III board

back to C3 board, main abc80 page.

History

2021-10-03: I re-created this page on my self-hosted web server.

2020-11-02: c1 - ada2p4 - abc80 - comment out and compile

tingo@kg-core1$ more output_files/abc80.fit.summary
Fitter Status : Successful - Mon Nov  2 19:21:24 2020
Quartus II 64-Bit Version : 13.1.4 Build 182 03/12/2014 SJ Web Edition
Revision Name : abc80
Top-level Entity Name : abc80
Family : Cyclone III
Device : EP3C25Q240C8
Timing Models : Final
Total logic elements : 8,135 / 24,624 ( 33 % )
    Total combinational functions : 7,829 / 24,624 ( 32 % )
    Dedicated logic registers : 1,827 / 24,624 ( 7 % )
Total registers : 1831
Total pins : 105 / 149 ( 70 % )
Total virtual pins : 0
Total memory bits : 100,352 / 608,256 ( 16 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 2 / 4 ( 50 % )

interesting.

2018-09-06: e1 - abc80-de1-18 - assign pins (from the .qsf file)

set_location_assignment PIN_152 -to clock_50
set_location_assignment PIN_39 -to ps2_dat
set_location_assignment PIN_43 -to ps2_clk
set_location_assignment PIN_56 -to vga_vs
set_location_assignment PIN_52 -to vga_hs
set_location_assignment PIN_50 -to vga_b[1]
set_location_assignment PIN_41 -to vga_g[0]
set_location_assignment PIN_44 -to vga_g[1]
set_location_assignment PIN_22 -to vga_r[0]
set_location_assignment PIN_38 -to vga_r[1]
set_location_assignment PIN_46 -to vga_b[0]
set_location_assignment PIN_232 -to uart_txd
set_location_assignment PIN_224 -to uart_rxd

compile and test. Interesting - I get a test picture. The colors are wrong, and the start position is off, but the picture is stable.

2018-09-06: e1 - abc80-18 - assign pins: (from the .qsf file)

set_location_assignment PIN_152 -to clkin
set_location_assignment PIN_39 -to ps2_kdata
set_location_assignment PIN_43 -to ps2_kclk
set_location_assignment PIN_38 -to vga_r[1]
set_location_assignment PIN_22 -to vga_r[0]
set_location_assignment PIN_44 -to vga_g[1]
set_location_assignment PIN_41 -to vga_g[0]
set_location_assignment PIN_50 -to vga_b[1]
set_location_assignment PIN_46 -to vga_b[0]
set_location_assignment PIN_56 -to vga_vs
set_location_assignment PIN_52 -to vga_hs

ok. Compile and test. I get something to the VGA monitor, because the OSD says "not optimum mode". But - no picture.

2018-09-05: e1 - abc80-18 - remove pins. removed 7-segment pins s7_0 and s7_1 from both the interface definition and the architecture section. Remove pins used for cassette interface

//          p1_a28,        // Proto1 (J11) pin 28
//          p1_a29,        // Proto1 (J11) pin 29
//          p1_a38,        // Proto1 (J11) pin 38

and

//   output        p1_a29;
//   output        p1_a28;
//   input         p1_a38;

and

   // Map the cassette port to some of the very few unclaimed (by the
   // CF card) pins on Prototype Connector 1.
//   assign     p1_a29 = cas_relay;
//   assign     p1_a28 = cas_output;
//   assign     cas_input = p1_a38;

//   assign     std_led[3] = cas_relay;
//   assign     std_led[4] = cas_output;

remove LED definitions, remove Ethernet (enet), remove CompactFlash (cf), and finally the result fits:

Fitter Status : Successful - Wed Sep  5 16:08:48 2018
Quartus II 32-bit Version : 13.1.4 Build 182 03/12/2014 SJ Web Edition
Revision Name : abc80
Top-level Entity Name : abc80
Family : Cyclone III
Device : EP3C25Q240C8
Timing Models : Final
Total logic elements : 5,237 / 24,624 ( 21 % )
    Total combinational functions : 5,061 / 24,624 ( 21 % )
    Dedicated logic registers : 1,133 / 24,624 ( 5 % )
Total registers : 1133
Total pins : 118 / 149 ( 79 % )
Total virtual pins : 0
Total memory bits : 237,568 / 608,256 ( 39 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 1 / 4 ( 25 % )

now to make it work.

2018-09-04: e1 - abc80-18 - I set up an abc80-18 project, based on the last release before the DE1 board releases. After fixing up the PLL's I got the code to compile. Changes

//   pll1 pll1 (
//          .inclk0 ( clkin ), // 50 MHz input clock
//          .c0 ( fast_clk ),     // x2/1 = 100 MHz output clock
//          .c1 ( cpu_clk_d ), // x1/2 =  25 MHz output clock
//          .e0 ( pld_clkout ) // External only output x1/2 = 25 MHz
//          );
   pll1 pll1 (
          .inclk0 ( clkin ),    // 50 MHz input clock
          .c0 ( fast_clk ),        // x2/1  = 100 MHz
          .c1 ( cpu_clk ),        // x1/2  =  25 MHz
          .c2 ( video_clk ),    // x3/8  =  18.75 MHz
          .locked ( pll1_locked )
          );

//   assign      cpu_clk = cpu_clk_d;

   // pld_clkfb is pld_clkout routed externally through a zero-skew buffer
//   pll2 pll2 (
//          .inclk0 ( pld_clkfb ), // 25 MHz input clock
//          .c0 ( video_clk )
//          );
   pll2 pll2 (
//          .inclk0 ( clock_24[0] ),    // 24 MHz input clock
          .inclk0 ( pld_clkfb ),    // 24 MHz input clock
          .c0 ( audio_clk ),    // x2/3 =  16 MHz
          .locked ( pll2_locked )
          );

but I still get errors about pins

Error (169282): There are 182 IO output pads in the design, but only 133 IO output pad locations available on the device.
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Error (171000): Can't fit design in device

ok.

2018-09-04: e1 - abc80 - ROM sizes

basic80.mif 256 x 16 (4096 bits)
chargen.mif 2048 x 8 (16384 bits)
fgcol.mif 512 x 4 (2048 bits)
keyboard.mif 2048 x 8 (16384 bits)
mmu.mif 1024 x 16 (16384 bits)
sddrom.mif 1024 x 8  (8192 bits)
videoram.mif 2048 x 8 (16384 bits)

in total 79872 bits, or 78 kbits. Plus the 32 kbyte abc80rom (256 kbits). Should be possible to fit all that into block RAM on the C3.

2018-09-04: e1 - I downloaded abc80-de1-18.zip, copied files and set up a project for the C3 board, initially without pin assignments. Tried to compile the project, failed at

Error (169282): There are 257 IO output pads in the design, but only 133 IO output pad locations available on the device.
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
Error (171000): Can't fit design in device

ok. Removed the dram assignments from abc80.v, and tried again, got

Error (169282): There are 219 IO output pads in the design, but only 133 IO output pad locations available on the device.
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Error (171000): Can't fit design in device

what else can I remove? removed gpio (gpio_0, gpio_1) assignments, got

Error (169282): There are 147 IO output pads in the design, but only 133 IO output pad locations available on the device.
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
Error (171000): Can't fit design in device

ok, try to remove 14 more pins. Removed 7-segment display assignments, let's see what happens.

Fitter Status : Successful - Tue Sep  4 14:40:25 2018
Quartus II 32-bit Version : 13.1.4 Build 182 03/12/2014 SJ Web Edition
Revision Name : abc80
Top-level Entity Name : abc80
Family : Cyclone III
Device : EP3C25Q240C8
Timing Models : Final
Total logic elements : 8,194 / 24,624 ( 33 % )
    Total combinational functions : 7,909 / 24,624 ( 32 % )
    Dedicated logic registers : 1,857 / 24,624 ( 8 % )
Total registers : 1861
Total pins : 141 / 149 ( 95 % )
Total virtual pins : 0
Total memory bits : 100,352 / 608,256 ( 16 % )
Embedded Multiplier 9-bit elements : 0 / 132 ( 0 % )
Total PLLs : 2 / 4 ( 50 % )

that worked nicely. assign clock_50 to pin 152 and recompile. Yes, still compiles successfully.

2018-08-24: c1 - I downloaded abc80-de1-18.zip, copied files and set up a project for the C3 board, initially without pin assignments. Tried to compile the project, failed at

Error (169282): There are 257 IO output pads in the design, but only 133 IO output pad locations available on the device.
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
Error (171000): Can't fit design in device

looking at the design, pins for dram and gpio are defined, but not used. Maybe that's the reason.