Kickstarter - Nandland Go Board - Your FPGA Playground

Project name: Nandland Go Board - Your FPGA Playground

  • FPGA: Lattice ICE40 HX1K vq100 - 1280 logic cells
  • flash: 1 Mb flash - for booting FPGA (bitstream storage?)
  • clock: 25 MHz onboard clock
  • connection: micro usb connector
  • switches: 4 x push buttons
  • indicators: 1 x PWR LED, 4 x user settable LEDs, dual 7-segment display
  • output: VGA connector
  • expansion: PMOD connector

blif - Berkeley Logic Interchange Format

pcf - physical constraints file - pin assignments (and clocks?)

tools in the open source toolchain:

[tingo@localhost ~]$ ls --color=never /usr/local/bin
arachne-pnr    iceboxdb.py     icebox_html  icebox_stat  icemulti  iceprog    yosys         yosys-filterlib
icebox_chipdb  icebox_diff     icebox_maps  icebox_vlog  icepack   icetime    yosys-abc     yosys-smtbmc
icebox_colbuf  icebox_explain  icebox.py    icebram      icepll    iceunpack  yosys-config

--- build flow ---

synthesize
place and route
convert to binary
program

Back to crowdfunding, FPGA page.

Links

nandland.com, IceStorm, Yosys, Lattice, github.com: arachne-pnr, icestorm, EDA Playground,

other links: fpga-vt - vt100 in VHDL, github.com: SimpleVOut, Cheap FPGA development boards, graywolf, qflow, Wolfgang Spraul's fpgatools, Verilog to Routing, Open Circuit Design, PDP2011, Configum FPGA module (Spartan-6), miniSpartan6+, Mercury DIP FPGA board (Spartan-3A), Hamsterworks wiki: FPGA course (VHDL),

more links: open-fpga-verilog-tutorial, FPGA peripherals, iceDAQ, Debian wiki: FPGA/Lattice, Xilinx - Torc, GHDL,

soft CPU: J2,

SoC: MiSoC,

cores: LiteEth, LiteSATA, LiteUSB,

local links

IceStorm, Arachne-pnr, Yosys,

History

2021-08-01: I re-created this page on my self-hosted web server.

2018-07-14: project 1 on FreeBSD - using tools from ports, try this synthesize

tingo@kg-core1$ yosys -Qp "synth_ice40 -blif Switches_To_LEDs.blif" Switches_To_LEDs.v > build_log.log

place and route

tingo@kg-core1$ arachne-pnr -d 1k -P vq100 -p  Switches_To_LEDs.pcf Switches_To_LEDs.blif -o Switches_To_LEDs.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif Switches_To_LEDs.blif...
prune...
read_pcf Switches_To_LEDs.pcf...
instantiate_io...
pack...

After packing:
IOs          8 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          0 / 1280
  DFF        0
  CARRY      0
  CARRY, DFF 0
  DFF PASS   0
  CARRY PASS 0
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 0

place_constraints...
promote_globals...
  promoted 0 nets
  0 globals
realize_constants...
place...
  initial wire length = 11
  at iteration #50: temp = 7.92282, wire length = 11
  final wire length = 11

After placement:
PIOs       5 / 72
PLBs       0 / 160
BRAMs      0 / 16

  place time 0.00s
route...
  pass 1, 0 shared.

After routing:
span_4     6 / 6944
span_12    0 / 1440

  route time 0.02s
write_txt Switches_To_LEDs.asc...

convert to binary

tingo@kg-core1$ icepack Switches_To_LEDs.asc Switches_To_LEDs.bin

program

tingo@kg-core1$ iceprog Switches_To_LEDs.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

does it work? yes it does.

2018-07-14: plugging the Nandland Go board into my FreeBSD workstation

tingo@kg-core1$ uname -a
FreeBSD kg-core1.kg4.no 10.4-STABLE FreeBSD 10.4-STABLE #1 r329982: Sun Feb 25 20:35:06 CET 2018     root@kg-core1.kg4.no:/usr/obj/usr/src/sys/GENERIC  amd64

from /var/log/messages

Jul 14 13:54:38 kg-core1 kernel: ugen3.4: <FTDI Dual RS232-HS> at usbus3
Jul 14 13:54:38 kg-core1 devd: Executing 'kldload -n uftdi'
Jul 14 13:54:38 kg-core1 devd: Executing 'kldload -n uftdi'
Jul 14 13:54:38 kg-core1 kernel: uftdi0: <Dual RS232-HS> on usbus3
Jul 14 13:54:38 kg-core1 kernel: uftdi1: <Dual RS232-HS> on usbus3
Jul 14 13:55:33 kg-core1 kernel: ugen3.4: <FTDI Dual RS232-HS> at usbus3 (disconnected)
Jul 14 13:55:33 kg-core1 kernel: uftdi0: at uhub8, port 2, addr 4 (disconnected)
Jul 14 13:55:33 kg-core1 kernel: uftdi1: at uhub8, port 2, addr 4 (disconnected)
Jul 14 13:55:34 kg-core1 kernel: ugen3.4: <FTDI Dual RS232-HS> at usbus3
Jul 14 13:55:34 kg-core1 kernel: uftdi0: <Dual RS232-HS> on usbus3
Jul 14 13:55:34 kg-core1 kernel: uftdi1: <Dual RS232-HS> on usbus3

and usbconfig says

root@kg-core1# usbconfig -d ugen3.4
ugen3.4: <FTDI Dual RS232-HS> at usbus3, cfg=0 md=HOST spd=HIGH (480Mbps) pwr=ON (500mA)

ok.

2017-04-26: with picocom I get a usable console on Mecrisp, so try to enter words.

create font  ok.
binary  ok.
0111111 , \ 0  ok.
0000110 , \ 1  ok.
1011011 , \ 2  ok.
1001111 , \ 3  ok.
100110 , \ 4  ok.
1101101 , \ 5  ok.
1111101 , \ 6  ok.
0000111 , \ 7  ok.
1111111 , \ 8  ok.
1101111 , \ 9  ok.
1110111 , \ A  ok.
1111100 , \ B  ok.
0111001 , \ C  ok.
1011110 , \ D  ok.
1111001 , \ E  ok.
1110001 , \ F  ok.
decimal  ok.

I messed up that one

: >seg ( u -- x ) 2* font + @ ;  ok.
: seg.x ( c -- )  ok.
dup  ok.
$F and >seg 7 lshift  ok.
swap  ok.
4 rshift $F and >seg  ok.
or $80 io! ;  ok.

more words

: ascii ( -- ) \ display keys on 7-seg until ESC is pressed  ok.
begin key dup seg.x 27 = until ;  ok.

and ascii is the "program". Run it

ascii

nothing is printed on the console, but the 7-segment display display the code of the key I press.

2017-04-26: I found Mecrisp-Ice via this blog post from jeelabs. Too interesting, I have to test it out.

[tingo@kg-elitebook mecrisp-ice]$ pwd
/zs/tingo/work/nandland_go/1_other/mecrisp-ice
[tingo@kg-elitebook mecrisp-ice]$ git clone https://github.com/zuloloxi/mecrisp-ice.git
Cloning into 'mecrisp-ice'...
remote: Counting objects: 183, done.
remote: Compressing objects: 100% (76/76), done.
remote: Total 183 (delta 100), reused 183 (delta 100), pack-reused 0
Receiving objects: 100% (183/183), 366.60 KiB | 574.00 KiB/s, done.
Resolving deltas: 100% (100/100), done.
Checking connectivity... done.

and my Go board is at

[tingo@kg-elitebook mecrisp-ice]$ ls -l /dev/ttyU*
crw-rw----. 1 root dialout 188, 0 Apr 26 16:18 /dev/ttyUSB0
crw-rw----. 1 root dialout 188, 1 Apr 26 16:18 /dev/ttyUSB1

ttyUSB0 and 1. program it

[tingo@kg-elitebook mecrisp-ice]$ sudo /usr/local/bin/iceprog mecrisp-ice/nandland/j1a.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32476
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

ok. Use screen to test it

[tingo@kg-elitebook ~]$ screen /dev/ttyUSB1 115200

and we get a staircase effect for lines. Not good. Try to use picocom instead:

[tingo@kg-elitebook Desktop]$ picocom -b 115200 /dev/ttyUSB1 --imap lfcrlf,crcrlf --omap delbs,crlf --send-cmd "ascii-xfr -s -l 30 -n"
picocom v1.7

port is        : /dev/ttyUSB1
flowcontrol    : none
baudrate is    : 115200
parity is      : none
databits are   : 8
escape is      : C-a
local echo is  : no
noinit is      : no
noreset is     : no
nolock is      : no
send_cmd is    : ascii-xfr -s -l 30 -n
receive_cmd is : rz -vv
imap is        : crcrlf,lfcrlf,
omap is        : crlf,delbs,
emap is        : crcrlf,delbs,

Terminal ready

this maps CR and LF so the staircase effect is avoided.

When I press reset I get

Mecrisp-Ice 0.8

and pressing enter gives

  ok.

haha.

2017-04-24: researching the ps2 pmod adapter. Perhaps I can solder up such an adapter. I have ps2 adapter for Arduino and other in my parts box (this, this).

2017-04-11: project 10: PONG. simulate, synthesize

[tingo@localhost project_10]$ yosys -Qp "synth_ice40 -blif Project10_Pong,blif" Project10_Pong_Top.v Debounce_Switch.v Pong_Paddle_Ctrl.v UART_RX.v VGA_Sync_Pulses.v Pong_Ball_Ctrl.v Pong_Top.v Sync_To_Count.v VGA_Sync_Porch.v > build_log.log

from build log

Warning: Resizing cell port Project10_Pong_Top.Pong_Inst.o_Blu_Video from 3 bits to 4 bits.
Warning: Resizing cell port Project10_Pong_Top.Pong_Inst.o_Grn_Video from 3 bits to 4 bits.
Warning: Resizing cell port Project10_Pong_Top.Pong_Inst.o_Red_Video from 3 bits to 4 bits.
Warning: Resizing cell port Project10_Pong_Top.VGA_Sync_Pulses_Inst.o_Row_Count from 0 bits to 10 bits.
Warning: Resizing cell port Project10_Pong_Top.VGA_Sync_Pulses_Inst.o_Col_Count from 0 bits to 10 bits.
Warning: Resizing cell port Project10_Pong_Top.UART_RX_Inst.o_RX_Byte from 0 bits to 8 bits.

10.27. Printing statistics.

=== Project10_Pong_Top ===

   Number of wires:                728
   Number of wire bits:           2013
   Number of public wires:         155
   Number of public wire bits:     551
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               1438
     SB_CARRY                      450
     SB_DFF                         11
     SB_DFFE                        31
     SB_DFFESR                     153
     SB_DFFESS                      12
     SB_DFFSR                       98
     SB_DFFSS                        2
     SB_LUT4                       681

10.28. Executing CHECK pass (checking for obvious problems).
checking module Project10_Pong_Top..
found and reported 0 problems.

10.29. Executing BLIF backend.

End of script. Logfile hash: 1edb91d285
CPU: user 2.91s system 0.04s, MEM: 55.49 MB total, 25.08 MB resident
Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)
Time spent: 22% 26x opt_expr (0 sec), 21% 26x opt_clean (0 sec), ...

place and route

[tingo@localhost project_10]$ arachne-pnr -d 1k -P vq100 -p Project10_Pong.pcf Project10_Pong.blif -o Project10_Pong.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif Project10_Pong.blif...
prune...
read_pcf Project10_Pong.pcf...
instantiate_io...
pack...

After packing:
IOs          17 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          989 / 1280
  DFF        144
  CARRY      327
  CARRY, DFF 163
  DFF PASS   28
  CARRY PASS 56
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted i_Clk$2, 307 / 307
  promoted $abc$7938$n923, 36 / 36
  promoted $abc$7938$n21, 35 / 35
  promoted $abc$7938$n19, 35 / 35
  promoted Pong_Inst.P2_Inst.w_Paddle_Count_En, 32 / 32
  promoted Pong_Inst.P1_Inst.w_Paddle_Count_En, 32 / 32
  promoted $abc$7938$n927, 37 / 37
  promoted $abc$7938$n290, 24 / 24
  promoted 8 nets
    4 sr/we
    3 cen/wclke
    1 clk
  8 globals
    4 sr/we
    3 cen/wclke
    1 clk
realize_constants...
  realized 1
place...
  initial wire length = 8526
  at iteration #50: temp = 9.11314, wire length = 6240
  at iteration #100: temp = 4.67816, wire length = 4582
  at iteration #150: temp = 1.95603, wire length = 2815
  at iteration #200: temp = 0.177329, wire length = 1940
  final wire length = 1866

After placement:
PIOs       17 / 72
PLBs       155 / 160
BRAMs      0 / 16

  place time 2.95s
route...
  pass 1, 5 shared.
  pass 2, 0 shared.

After routing:
span_4     883 / 6944
span_12    169 / 1440

  route time 1.05s
write_txt Project10_Pong.asc...

convert to binary

[tingo@localhost project_10]$ icepack Project10_Pong.asc Project10_Pong.bin

program

[tingo@localhost project_10]$ sudo /usr/local/bin/iceprog Project10_Pong.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

Testing. Hook up a VGA monitor, screen to /dev/ttyUSB1

[tingo@localhost ~]$ screen /dev/ttyUSB1 115200

and check that it works. Yes it does. It is a bit hard to both start the game (press a key in the serial window) and play it for both players at the same time.

2017-04-10: project 9 - VGA introduction. simulate - it works, not self-checking so just some signal waves to look at.

synthesize

[tingo@localhost project_9]$ yosys -Qp "synth_ice40 -blif VGA_Test_Patterns.blif" VGA_Test_Patterns_Top.v Binary_To_7Segment.v Test_Pattern_Gen.v UART_TX.v VGA_Sync_Pulses.v UART_RX.v VGA_Sync_Porch.v > build_log.log

note: Sync_To_Count.v is included in Test_Pattern_Gen.v so don't include it on the command line.

from build log

8.27. Printing statistics.

=== VGA_Test_Patterns_Top ===

   Number of wires:                525
   Number of wire bits:           1055
   Number of public wires:         150
   Number of public wire bits:     357
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                717
     SB_CARRY                      221
     SB_DFF                         12
     SB_DFFE                        59
     SB_DFFESR                      33
     SB_DFFSR                       36
     SB_DFFSS                        2
     SB_LUT4                       354

8.28. Executing CHECK pass (checking for obvious problems).
checking module VGA_Test_Patterns_Top..
found and reported 0 problems.

8.29. Executing BLIF backend.

End of script. Logfile hash: 58b94e2e7a
CPU: user 2.51s system 0.03s, MEM: 52.72 MB total, 22.13 MB resident
Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)
Time spent: 22% 27x opt_expr (0 sec), 19% 24x opt_merge (0 sec), ...

place and route

[tingo@localhost project_9]$ arachne-pnr -d 1k -P vq100 -p VGA_Test_Patterns.pcf VGA_Test_Patterns.blif -o VGA_Test_Patterns.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif VGA_Test_Patterns.blif...
prune...
read_pcf VGA_Test_Patterns.pcf...
instantiate_io...
pack...

After packing:
IOs          28 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          604 / 1280
  DFF        128
  CARRY      240
  CARRY, DFF 14
  DFF PASS   34
  CARRY PASS 47
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted i_Clk$2, 142 / 142
  promoted VGA_Sync_Porch_Inst.UUT.w_Frame_Start, 23 / 23
  promoted Test_Pattern_Gen_Inst.UUT.w_Frame_Start, 23 / 23
  promoted $abc$6028$n5, 11 / 20
  promoted $abc$6028$n13, 11 / 11
  promoted $abc$6028$n753, 9 / 9
  promoted $abc$6028$n742, 9 / 9
  promoted $abc$6028$n729, 9 / 9
  promoted 8 nets
    4 sr/we
    3 cen/wclke
    1 clk
  8 globals
    4 sr/we
    3 cen/wclke
    1 clk
realize_constants...
  realized 1
place...
  initial wire length = 4654
  at iteration #50: temp = 6.07707, wire length = 3428
  at iteration #100: temp = 3.28381, wire length = 2375
  at iteration #150: temp = 1.30438, wire length = 1523
  at iteration #200: temp = 0.0164092, wire length = 1114
  final wire length = 1103

After placement:
PIOs       22 / 72
PLBs       123 / 160
BRAMs      0 / 16

  place time 1.76s
route...
  pass 1, 0 shared.

After routing:
span_4     537 / 6944
span_12    123 / 1440

  route time 0.73s
write_txt VGA_Test_Patterns.asc...

convert to binary

[tingo@localhost project_9]$ icepack VGA_Test_Patterns.asc VGA_Test_Patterns.bin

program

[tingo@localhost project_9]$ sudo /usr/local/bin/iceprog VGA_Test_Patterns.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

test that it works. Yes, it does.

2017-04-10: project 8 - UART part 2: Transmit data to computer.

Simulate - running the predefined simulation works. when I try to extend the testbench to test more values, the TB code times out after the first testcase is finished. Not good.

original part - works

      // Tell UART to send a command (exercise TX)
      @(posedge r_Clock);
      @(posedge r_Clock);
      r_TX_DV   <= 1'b1;
      r_TX_Byte <= 8'h3F;
      @(posedge r_Clock);
      r_TX_DV <= 1'b0;

      // Check that the correct command was received
      @(posedge w_RX_DV);
      if (w_RX_Byte == 8'h3F)
        $display("Test Passed - 3fh Byte Received");
      else
        $display("Test Failed - Incorrect Byte Received");

my addition (after the original part) - times out

      @(posedge r_Clock);
      @(posedge r_Clock);
      r_TX_DV   <= 1'b1;
      r_TX_Byte <= 8'h55;
      @(posedge r_Clock);
      r_TX_DV <= 1'b0;

      @(posedge r_Clock);
      @(posedge r_Clock);
      @(posedge w_RX_DV);
      if (w_RX_Byte == 8'h55)
        $display("Test Passed - 55h Byte Received");
      else
        $display("Test Failed - Incorrect Byte Received");

why?

synthesize

[tingo@localhost project_8]$ yosys -Qp "synth_ice40 -blif UART_Loopback.blif" UART_Loopback_Top.v UART_TX.v UART_RX.v Binary_To_7Segment.v > build_log.log

from build log

5.27. Printing statistics.

=== UART_Loopback_Top ===

   Number of wires:                194
   Number of wire bits:            295
   Number of public wires:          74
   Number of public wire bits:     141
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                210
     SB_CARRY                       24
     SB_DFFE                        55
     SB_DFFSR                        6
     SB_LUT4                       125

5.28. Executing CHECK pass (checking for obvious problems).
checking module UART_Loopback_Top..
found and reported 0 problems.

5.29. Executing BLIF backend.

End of script. Logfile hash: 18d0e1303d
CPU: user 0.97s system 0.02s, MEM: 54.27 MB total, 24.41 MB resident
Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)
Time spent: 18% 23x opt_expr (0 sec), 14% 20x opt_merge (0 sec), ...

place and route

[tingo@localhost project_8]$ arachne-pnr -d 1k -P vq100 -p UART_Loopback.pcf UART_Loopback.blif -o UART_Loopback.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif UART_Loopback.blif...
prune...
read_pcf UART_Loopback.pcf...
instantiate_io...
pack...

After packing:
IOs          17 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          165 / 1280
  DFF        61
  CARRY      31
  CARRY, DFF 0
  DFF PASS   16
  CARRY PASS 10
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted i_Clk$2, 61 / 61
  promoted $abc$3214$n314, 9 / 9
  promoted $abc$3214$n119, 8 / 8
  promoted $abc$3214$n108, 8 / 8
  promoted 4 nets
    3 cen/wclke
    1 clk
  4 globals
    3 cen/wclke
    1 clk
realize_constants...
  realized 1
place...
  initial wire length = 2035
  at iteration #50: temp = 6.34391, wire length = 1379
  at iteration #100: temp = 3.42799, wire length = 871
  at iteration #150: temp = 1.36165, wire length = 515
  at iteration #200: temp = 0.213718, wire length = 310
  final wire length = 289

After placement:
PIOs       14 / 72
PLBs       48 / 160
BRAMs      0 / 16

  place time 0.50s
route...
  pass 1, 0 shared.

After routing:
span_4     129 / 6944
span_12    22 / 1440

  route time 0.18s
write_txt UART_Loopback.asc...

convert to binary

[tingo@localhost project_8]$ icepack UART_Loopback.asc UART_Loopback.bin

program

[tingo@localhost project_8]$ sudo /usr/local/bin/iceprog UART_Loopback.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

now test it. Run screen to ttyUSB1

[tingo@localhost ~]$ screen /dev/ttyUSB1 115200

and type into it. does it echo? Yes it does. and also writes ASCII vaules (in hex) to the seven segment display on the go board.

2017-04-07: project 7 - UART part 1: Receive data from computer.

simulate - (with EDA playground) I ran the testbench for the UART_RX module with several values (00, ff, 55) in addition to the original 37h. All worked nicely.

synthesize

[tingo@localhost project_7]$ yosys -Qp "synth_ice40 -blif UART_RX_To_7_Seg.blif" UART_RX_To_7_Seg_Top.v UART_RX.v Binary_To_7Segment.v > build_log.log
from build log
4.27. Printing statistics.

=== UART_RX_To_7_Seg_Top ===

   Number of wires:                124
   Number of wire bits:            190
   Number of public wires:          58
   Number of public wire bits:     108
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                123
     SB_CARRY                       11
     SB_DFFE                        33
     SB_DFFSR                        3
     SB_LUT4                        76

4.28. Executing CHECK pass (checking for obvious problems).
checking module UART_RX_To_7_Seg_Top..
found and reported 0 problems.

4.29. Executing BLIF backend.

End of script. Logfile hash: 37696e6812
CPU: user 0.76s system 0.03s, MEM: 44.86 MB total, 14.83 MB resident
Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)
Time spent: 18% 22x opt_expr (0 sec), 16% 11x read_verilog (0 sec), ...

place and route

[tingo@localhost project_7]$ arachne-pnr -d 1k -P vq100 -p UART_RX_To_7_Seg.pcf UART_RX_To_7_Seg.blif -o UART_RX_To_7_Seg.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif UART_RX_To_7_Seg.blif...
prune...
read_pcf UART_RX_To_7_Seg.pcf...
instantiate_io...
pack...

After packing:
IOs          16 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          94 / 1280
  DFF        36
  CARRY      14
  CARRY, DFF 0
  DFF PASS   8
  CARRY PASS 4
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted i_Clk$2, 36 / 36
  promoted $abc$2356$n53, 8 / 8
  promoted 2 nets
    1 cen/wclke
    1 clk
  2 globals
    1 cen/wclke
    1 clk
realize_constants...
  realized 1
place...
  initial wire length = 1160
  at iteration #50: temp = 5.74128, wire length = 764
  at iteration #100: temp = 3.26564, wire length = 522
  at iteration #150: temp = 1.36543, wire length = 308
  at iteration #200: temp = 0.0819077, wire length = 177
  final wire length = 175

After placement:
PIOs       12 / 72
PLBs       32 / 160
BRAMs      0 / 16

  place time 0.25s
route...
  pass 1, 0 shared.

After routing:
span_4     82 / 6944
span_12    20 / 1440

  route time 0.11s
write_txt UART_RX_To_7_Seg.asc...

convert to binary

[tingo@localhost project_7]$ icepack UART_RX_To_7_Seg.asc UART_RX_To_7_Seg.bin

program

[tingo@localhost project_7]$ sudo /usr/local/bin/iceprog UART_RX_To_7_Seg.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

does it work? I set up screen to run at 115200 and port /dev/ttyUSB1:

[tingo@localhost ~]$ screen /dev/ttyUSB1 115200

and it works. Very nice!

2017-04-06: no work done on the FPGA course this day.

2017-04-05:project 6 - How to simulate your FPGA designs.

Simulation with EDA playground: you need to log in to run the simulator, you need to select a non-commercial simulator (or register).

synthesize

[tingo@localhost project_6]$ yosys -Qp "synth_ice40 -blif LED_Blink.blif" LED_Blink_Top.v LED_Blink.v > build_log.log
from build log
3.27. Printing statistics.

=== LED_Blink_Top ===

   Number of wires:                 63
   Number of wire bits:            342
   Number of public wires:          12
   Number of public wire bits:     105
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                327
     SB_CARRY                       90
     SB_DFFE                         3
     SB_DFFESR                       3
     SB_DFFSR                       93
     SB_LUT4                       138

3.28. Executing CHECK pass (checking for obvious problems).
checking module LED_Blink_Top..
found and reported 0 problems.

3.29. Executing BLIF backend.

End of script. Logfile hash: 5853711202
CPU: user 0.44s system 0.01s, MEM: 42.77 MB total, 12.82 MB resident
Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)
Time spent: 27% 10x read_verilog (0 sec), 14% 15x opt_expr (0 sec), ...

place and route

[tingo@localhost project_6]$ arachne-pnr -d 1k -P vq100 -p LED_Blink.pcf LED_Blink.blif -o LED_Blink.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif LED_Blink.blif...
prune...
read_pcf LED_Blink.pcf...
instantiate_io...
pack...

After packing:
IOs          5 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          144 / 1280
  DFF        12
  CARRY      6
  CARRY, DFF 87
  DFF PASS   0
  CARRY PASS 3
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted i_Clk$2, 99 / 99
  promoted $abc$1261$n5, 32 / 32
  promoted $abc$1261$n3, 32 / 32
  promoted $abc$1261$n1, 32 / 32
  promoted 4 nets
    3 sr/we
    1 clk
  4 globals
    3 sr/we
    1 clk
realize_constants...
  realized 1
place...
  initial wire length = 1730
  at iteration #50: temp = 13.5904, wire length = 1090
  at iteration #100: temp = 6.60934, wire length = 607
  at iteration #150: temp = 2.13834, wire length = 335
  at iteration #200: temp = 0.0269006, wire length = 230
  final wire length = 230

After placement:
PIOs       7 / 72
PLBs       34 / 160
BRAMs      0 / 16

  place time 0.22s
route...
  pass 1, 0 shared.

After routing:
span_4     44 / 6944
span_12    17 / 1440

  route time 0.10s
write_txt LED_Blink.asc...

convert to binary

[tingo@localhost project_6]$ icepack LED_Blink.asc LED_Blink.bin

program

[tingo@localhost project_6]$ sudo /usr/local/bin/iceprog LED_Blink.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

and LED 1 doesn't blink (it is not supposed to, since it is not assigned). It works! Changing the code so LED1 is assigned and re-synthesize also works.

2017-04-05:project 5 - Seven Segment display. synthesize

[tingo@localhost project_5]$ yosys -Qp "synth_ice40 -blif P_7_Segment.blif" Project_7_Segment_Top.v Binary_To_7Segment.v Debounce_Switch.v > build_log.log
from build log
4.27. Printing statistics.

=== Project_7_Segment_Top ===

   Number of wires:                 60
   Number of wire bits:            160
   Number of public wires:          34
   Number of public wire bits:      63
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                109
     SB_CARRY                       31
     SB_DFF                          1
     SB_DFFE                         8
     SB_DFFESR                       5
     SB_DFFSR                       17
     SB_LUT4                        47

4.28. Executing CHECK pass (checking for obvious problems).
checking module Project_7_Segment_Top..
found and reported 0 problems.

4.29. Executing BLIF backend.

End of script. Logfile hash: 87ef62f277
CPU: user 0.46s system 0.02s, MEM: 43.05 MB total, 13.11 MB resident
Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)
Time spent: 26% 11x read_verilog (0 sec), 14% 20x opt_expr (0 sec), ...

place and route

[tingo@localhost project_5]$ arachne-pnr -d 1k -P vq100 -p p_7_Segment.pcf P_7_Segment.blif -o P_7_Segment.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif P_7_Segment.blif...
prune...
read_pcf p_7_Segment.pcf...
instantiate_io...
pack...

After packing:
IOs          9 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          68 / 1280
  DFF        15
  CARRY      18
  CARRY, DFF 16
  DFF PASS   2
  CARRY PASS 4
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted i_Clk$2, 31 / 31
  promoted $abc$1119$n3, 20 / 20
  promoted 2 nets
    1 sr/we
    1 clk
  2 globals
    1 sr/we
    1 clk
realize_constants...
  realized 1
place...
  initial wire length = 841
  at iteration #50: temp = 8.58574, wire length = 459
  at iteration #100: temp = 3.9777, wire length = 327
  at iteration #150: temp = 1.16144, wire length = 172
  final wire length = 147

After placement:
PIOs       9 / 72
PLBs       23 / 160
BRAMs      0 / 16

  place time 0.12s
route...
  pass 1, 0 shared.

After routing:
span_4     41 / 6944
span_12    13 / 1440

  route time 0.08s
write_txt P_7_Segment.asc...

convert to binary

[tingo@localhost project_5]$ icepack P_7_Segment.asc P_7_Segment.bin

program

[tingo@localhost project_5]$ sudo /usr/local/bin/iceprog P_7_Segment.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

and - it works. The rightmost 7 segment display count from zero to nine when button 1 is pressed (one count per press).

2017-04-05: project 4 - debounce a switch. continue from yesterday. synthesize

[tingo@localhost project_4]$ yosys -Qp "synth_ice40 -blif Debounce_Project.blif" Debounce_Project_Top.v Debounce_Switch.v > build_log.log
from the build log
-- Parsing `Debounce_Project_Top.v' using frontend `verilog' --

1. Executing Verilog-2005 frontend.
Parsing Verilog input from `Debounce_Project_Top.v' to AST representation.
Generating RTLIL representation for module `\Debounce_Project_Top'.
Successfully finished Verilog frontend.

-- Parsing `Debounce_Switch.v' using frontend `verilog' --

2. Executing Verilog-2005 frontend.
Parsing Verilog input from `Debounce_Switch.v' to AST representation.
Generating RTLIL representation for module `\Debounce_Switch'.
Successfully finished Verilog frontend.

-- Running command `synth_ice40 -blif Debounce_Project.blif' --
[...]
3.2. Executing HIERARCHY pass (managing design hierarchy).

3.2.1. Finding top of design hierarchy..
root of   0 design levels: Debounce_Switch     
root of   1 design levels: Debounce_Project_Top
Automatically selected Debounce_Project_Top as design top module.
[...]
3.7.6. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port B of cell Debounce_Project_Top.$techmap\Debounce_Inst.$add$Debounce_Switch.v:20$12 ($add).
Removed top 14 bits (of 32) from port Y of cell Debounce_Project_Top.$techmap\Debounce_Inst.$add$Debounce_Switch.v:20$12 ($add).
Removed top 14 bits (of 32) from port B of cell Debounce_Project_Top.$techmap\Debounce_Inst.$lt$Debounce_Switch.v:19$10 ($lt).
Removed top 14 bits (of 32) from wire Debounce_Project_Top.$techmap\Debounce_Inst.$add$Debounce_Switch.v:20$12_Y.
[...]
3.7.7. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module Debounce_Project_Top:
  creating $macc model for $techmap\Debounce_Inst.$add$Debounce_Switch.v:20$12 ($add).
  creating $alu model for $macc $techmap\Debounce_Inst.$add$Debounce_Switch.v:20$12.
  creating $alu model for $techmap\Debounce_Inst.$lt$Debounce_Switch.v:19$10 ($lt): new $alu
  creating $alu model for $techmap\Debounce_Inst.$eq$Debounce_Switch.v:23$13 ($eq): merged with $techmap\Debounce_Inst.$lt$Debounce_Switch.v:19$10.
  creating $alu cell for $techmap\Debounce_Inst.$lt$Debounce_Switch.v:19$10, $techmap\Debounce_Inst.$eq$Debounce_Switch.v:23$13: $auto$alumacc.cc:470:replace_alu$36
  creating $alu cell for $techmap\Debounce_Inst.$add$Debounce_Switch.v:20$12: $auto$alumacc.cc:470:replace_alu$43
  created 2 $alu and 0 $macc cells.
[...]
3.13.6. Continuing TECHMAP pass.
Mapping Debounce_Project_Top.$auto$alumacc.cc:470:replace_alu$43 using $paramod\_80_ice40_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=1\B_WIDTH=18\Y_WIDTH=18.
Mapping Debounce_Project_Top.$procmux$28 ($mux) with simplemap.
Mapping Debounce_Project_Top.$procdff$32 ($dff) with simplemap.
Mapping Debounce_Project_Top.$procdff$33 ($dff) with simplemap.
Mapping Debounce_Project_Top.$techmap\Debounce_Inst.$procdff$30 ($dff) with simplemap.
Mapping Debounce_Project_Top.$techmap\Debounce_Inst.$procdff$31 ($dff) with simplemap.
Mapping Debounce_Project_Top.$techmap\Debounce_Inst.$procmux$25 ($mux) with simplemap.
Mapping Debounce_Project_Top.$techmap\Debounce_Inst.$procmux$22 ($mux) with simplemap.
Mapping Debounce_Project_Top.$techmap\Debounce_Inst.$procmux$19 ($mux) with simplemap.
Mapping Debounce_Project_Top.$techmap\Debounce_Inst.$logic_and$Debounce_Switch.v:19$11 ($logic_and) with simplemap.
Mapping Debounce_Project_Top.$techmap\Debounce_Inst.$nex$Debounce_Switch.v:19$9 ($nex) with simplemap.
Mapping Debounce_Project_Top.$techmap$auto$alumacc.cc:470:replace_alu$36.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$99 ($xor) with simplemap.
Mapping Debounce_Project_Top.$techmap$auto$alumacc.cc:470:replace_alu$36.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$98 ($mux) with simplemap.
Mapping Debounce_Project_Top.$techmap$auto$alumacc.cc:470:replace_alu$36.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$97 ($not) with simplemap.
Mapping Debounce_Project_Top.$auto$alumacc.cc:470:replace_alu$36.B_conv ($pos) with simplemap.
Mapping Debounce_Project_Top.$auto$alumacc.cc:470:replace_alu$36.A_conv ($pos) with simplemap.
Mapping Debounce_Project_Top.$techmap$auto$alumacc.cc:470:replace_alu$43.$xor$/usr/local/bin/../share/yosys/ice40/arith_map.v:68$127 ($xor) with simplemap.
Mapping Debounce_Project_Top.$techmap$auto$alumacc.cc:470:replace_alu$43.$ternary$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$126 ($mux) with simplemap.
Mapping Debounce_Project_Top.$techmap$auto$alumacc.cc:470:replace_alu$43.$not$/usr/local/bin/../share/yosys/ice40/arith_map.v:42$125 ($not) with simplemap.
Mapping Debounce_Project_Top.$auto$alumacc.cc:470:replace_alu$43.B_conv ($pos) with simplemap.
Mapping Debounce_Project_Top.$auto$alumacc.cc:470:replace_alu$43.A_conv ($pos) with simplemap.
No more expansions possible.
[...]
3.22.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$399' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$400 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$399' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$397' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$398 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$397' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$395' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$396 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$395' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$393' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$394 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$393' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$391' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$392 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$391' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$389' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$390 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$389' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$387' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$388 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$387' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$385' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$386 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$385' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$383' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$384 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$383' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$381' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$382 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$381' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$379' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$380 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$379' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$377' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$378 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$377' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$375' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$376 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$375' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$373' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$374 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$373' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$371' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$372 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$371' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$369' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$370 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$369' from module `\Debounce_Project_Top'.
  Cell `$auto$ice40_ffssr.cc:106:execute$367' is identical to cell `$auto$ice40_ffssr.cc:106:execute$401'.
    Redirecting output \Y: $auto$rtlil.cc:1733:NotGate$368 = $auto$rtlil.cc:1733:NotGate$402
    Removing $_NOT_ cell `$auto$ice40_ffssr.cc:106:execute$367' from module `\Debounce_Project_Top'.
  Cell `$auto$simplemap.cc:85:simplemap_bitop$331' is identical to cell `$auto$simplemap.cc:85:simplemap_bitop$321'.
    Redirecting output \Y: $auto$simplemap.cc:250:simplemap_eqne$329 [0] = $auto$simplemap.cc:250:simplemap_eqne$319
    Removing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$331' from module `\Debounce_Project_Top'.
Removed a total of 18 cells.
[...]
3.24.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + dch -f 
ABC: + if 
ABC: + mfs2 
ABC: + lutpack -S 1 
ABC: + write_blif <abc-temp-dir>/output.blif 

3.24.1.2. Re-integrating ABC results.
ABC RESULTS:              $lut cells:       22
ABC RESULTS:        internal signals:       35
ABC RESULTS:           input signals:       23
ABC RESULTS:          output signals:        6
Removing temp directory.
Removed 0 unused cells and 41 unused wires.
[...]
3.27. Printing statistics.

=== Debounce_Project_Top ===

   Number of wires:                 26
   Number of wire bits:            108
   Number of public wires:          11
   Number of public wire bits:      28
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 78
     SB_CARRY                       29
     SB_DFF                          1
     SB_DFFE                         2
     SB_DFFESR                       1
     SB_DFFSR                       17
     SB_LUT4                        28

3.28. Executing CHECK pass (checking for obvious problems).
checking module Debounce_Project_Top..
found and reported 0 problems.

3.29. Executing BLIF backend.

End of script. Logfile hash: 8a86ed1668
CPU: user 0.31s system 0.01s, MEM: 41.72 MB total, 11.86 MB resident
Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)
Time spent: 37% 10x read_verilog (0 sec), 11% 20x opt_expr (0 sec), ...

place and route

[tingo@localhost project_4]$ arachne-pnr -d 1k -P vq100 -p Debounce_Project.pcf Debounce_Project.blif -o Debounce_Project.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif Debounce_Project.blif...
prune...
read_pcf Debounce_Project.pcf...
instantiate_io...
pack...

After packing:
IOs          3 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          47 / 1280
  DFF        6
  CARRY      16
  CARRY, DFF 15
  DFF PASS   2
  CARRY PASS 3
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted i_Clk$2, 21 / 21
  promoted $abc$406$n1, 20 / 20
  promoted 2 nets
    1 sr/we
    1 clk
  2 globals
    1 sr/we
    1 clk
realize_constants...
  realized 1
place...
  initial wire length = 513
  at iteration #50: temp = 8.24419, wire length = 250
  at iteration #100: temp = 3.44706, wire length = 152
  at iteration #150: temp = 0.377825, wire length = 81
  final wire length = 73

After placement:
PIOs       4 / 72
PLBs       13 / 160
BRAMs      0 / 16

  place time 0.05s
route...
  pass 1, 0 shared.

After routing:
span_4     16 / 6944
span_12    4 / 1440

  route time 0.03s
write_txt Debounce_Project.asc...

convert to binary

[tingo@localhost project_4]$ icepack Debounce_Project.asc Debounce_Project.bin

program

[tingo@localhost project_4]$ sudo /usr/local/bin/iceprog Debounce_Project.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

works? yes!

2017-04-04: project 4 - debounce a switch. Only got as fara as watching the video today.

2017-04-04: project 3 - Registers and clocks. synthesize

[tingo@localhost project_3]$ yosys -Qp "synth_ice40 -blif Clocked_Logic_Intro.blif" Clocked_Logic_Intro.v
[...]
2.3.3. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:7$7'.
  Set init value: \r_Switch_1 = 1'0
Found init rule in `\Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:6$6'.
  Set init value: \r_LED_1 = 1'0
[...]
2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:7$7'.
     1/1: $1\r_Switch_1[0:0]
Creating decoders for process `\Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:6$6'.
     1/1: $1\r_LED_1[0:0]
Creating decoders for process `\Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:10$1'.
     1/2: $0\r_Switch_1[0:0]
     2/2: $0\r_LED_1[0:0]
[...]
2.3.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\Clocked_Logic_Intro.\r_LED_1' using process `\Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:10$1'.
  created $dff cell `$procdff$11' with positive edge clock.
Creating register for signal `\Clocked_Logic_Intro.\r_Switch_1' using process `\Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:10$1'.
  created $dff cell `$procdff$12' with positive edge clock.

2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:7$7'.
Removing empty process `Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:6$6'.
Found and cleaned up 1 empty switch in `\Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:10$1'.
Removing empty process `Clocked_Logic_Intro.$proc$Clocked_Logic_Intro.v:10$1'.
Cleaned up 1 empty switch.
[...]
2.7.2. Executing OPT_EXPR pass (perform const folding).
Replacing $eq cell `$eq$Clocked_Logic_Intro.v:17$2' in module `Clocked_Logic_Intro' with inverter.
Replacing $eq cell `$eq$Clocked_Logic_Intro.v:17$3' (1) in module `\Clocked_Logic_Intro' with constant driver `$eq$Clocked_Logic_Intro.v:17$3_Y = \r_Switch_1'.
[...]
2.16. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
Selected cell types for direct conversion:
  $_DFF_PP1_ -> $__DFFE_PP1
  $_DFF_PP0_ -> $__DFFE_PP0
  $_DFF_PN1_ -> $__DFFE_PN1
  $_DFF_PN0_ -> $__DFFE_PN0
  $_DFF_NP1_ -> $__DFFE_NP1
  $_DFF_NP0_ -> $__DFFE_NP0
  $_DFF_NN1_ -> $__DFFE_NN1
  $_DFF_NN0_ -> $__DFFE_NN0
  $_DFF_N_ -> $_DFFE_NP_
  $_DFF_P_ -> $_DFFE_PP_
Transforming FF to FF+Enable cells in module Clocked_Logic_Intro:
  converting $_DFF_P_ cell $auto$simplemap.cc:420:simplemap_dff$67 to $_DFFE_PP_ for $0\r_LED_1[0:0] -> \r_LED_1.
[...]
2.18. Executing OPT_EXPR pass (perform const folding).
Replacing $_XOR_ cell `$auto$simplemap.cc:85:simplemap_bitop$73' (?0) in module `\Clocked_Logic_Intro' with constant driver `$auto$simplemap.cc:250:simplemap_eqne$71 = $logic_and$Clocked_Logic_Intro.v:17$4_Y'.
Replacing $_MUX_ cell `$auto$simplemap.cc:277:simplemap_mux$66' (x??) in module `\Clocked_Logic_Intro' with constant driver `$0\r_LED_1[0:0] = $not$Clocked_Logic_Intro.v:19$5_Y'.
[...]
2.20. Executing ICE40_FFINIT pass (implement FF init values).
Handling FF init values in Clocked_Logic_Intro.
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$68 (SB_DFF): \r_Switch_1 = 0
FF init value for cell $auto$simplemap.cc:420:simplemap_dff$67 (SB_DFFE): \r_LED_1 = 0
[...]
2.24.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/yosys-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lut <abc-temp-dir>/lutdefs.txt 
ABC: + strash 
ABC: + ifraig 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + dch -f 
ABC: + if 
ABC: + mfs2 
ABC: + lutpack -S 1 
ABC: + write_blif <abc-temp-dir>/output.blif 

2.24.1.2. Re-integrating ABC results.
ABC RESULTS:              $lut cells:        4
ABC RESULTS:        internal signals:        1
ABC RESULTS:           input signals:        3
ABC RESULTS:          output signals:        2
Removing temp directory.
Removed 0 unused cells and 6 unused wires.
[...]
2.27. Printing statistics.

=== Clocked_Logic_Intro ===

   Number of wires:                  7
   Number of wire bits:              7
   Number of public wires:           5
   Number of public wire bits:       5
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     SB_DFF                          1
     SB_DFFE                         1
     SB_LUT4                         2

2.28. Executing CHECK pass (checking for obvious problems).
checking module Clocked_Logic_Intro..
found and reported 0 problems.

2.29. Executing BLIF backend.

End of script. Logfile hash: 8edbed9de4
CPU: user 0.19s system 0.02s, MEM: 41.21 MB total, 11.40 MB resident
Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)
Time spent: 58% 9x read_verilog (0 sec), 13% 1x share (0 sec), ...

place and route

[tingo@localhost project_3]$ arachne-pnr -d 1k -P vq100 -p Clocked_Logic_Intro.pcf Clocked_Logic_Intro.blif -o Clocked_Logic_Intro.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif Clocked_Logic_Intro.blif...
prune...
read_pcf Clocked_Logic_Intro.pcf...
Clocked_Logic_Intro.pcf:11: fatal error: unknown command `create_clock'

ok, arachne-pnr doesn't support timing info. How about without?

[tingo@localhost project_3]$ arachne-pnr -d 1k -P vq100 -p Clocked_Logic_Intro.pcf Clocked_Logic_Intro.blif -o Clocked_Logic_Intro.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif Clocked_Logic_Intro.blif...
prune...
read_pcf Clocked_Logic_Intro.pcf...
instantiate_io...
pack...

After packing:
IOs          3 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          3 / 1280
  DFF        2
  CARRY      0
  CARRY, DFF 0
  DFF PASS   1
  CARRY PASS 0
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted 0 nets
  0 globals
realize_constants...
place...
  initial wire length = 83
  at iteration #50: temp = 5.16715, wire length = 41
  at iteration #100: temp = 2.16049, wire length = 37
  at iteration #150: temp = 0.00312765, wire length = 25
  final wire length = 25

After placement:
PIOs       3 / 72
PLBs       2 / 160
BRAMs      0 / 16

  place time 0.00s
route...
  pass 1, 0 shared.

After routing:
span_4     5 / 6944
span_12    3 / 1440

  route time 0.01s
write_txt Clocked_Logic_Intro.asc...
well, it didn't produce any error messages at least.

convert to binary

[tingo@localhost project_3]$ icepack Clocked_Logic_Intro.asc Clocked_Logic_Intro.bin

program

[tingo@localhost project_3]$ sudo /usr/local/bin/iceprog Clocked_Logic_Intro.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

does it work? - yes it does.

2017-04-04: project 2 - and gate. synthesize

[tingo@localhost project_2]$ yosys -Qp "synth_ice40 -blif And_Gate_Project.blif" And_Gate_Project.v

-- Parsing `And_Gate_Project.v' using frontend `verilog' --

1. Executing Verilog-2005 frontend.
Parsing Verilog input from `And_Gate_Project.v' to AST representation.
Generating RTLIL representation for module `\And_Gate_Project'.
Successfully finished Verilog frontend.

-- Running command `synth_ice40 -blif And_Gate_Project.blif' --

2. Executing SYNTH_ICE40 pass.
[...]
2.27. Printing statistics.

=== And_Gate_Project ===

   Number of wires:                  3
   Number of wire bits:              3
   Number of public wires:           3
   Number of public wire bits:       3
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     SB_LUT4                         1

2.28. Executing CHECK pass (checking for obvious problems).
checking module And_Gate_Project..
found and reported 0 problems.

2.29. Executing BLIF backend.

End of script. Logfile hash: b9fb6e998e
CPU: user 0.18s system 0.01s, MEM: 41.19 MB total, 11.32 MB resident
Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)
Time spent: 59% 9x read_verilog (0 sec), 14% 1x share (0 sec), ...

place and route

[tingo@localhost project_2]$ arachne-pnr -d 1k -P vq100 -p And_Gate_Project.pcf And_Gate_Project.blif And_Gate_Project.asc
fatal error: too many command-line arguments

missing a switch there

[tingo@localhost project_2]$ arachne-pnr -d 1k -P vq100 -p And_Gate_Project.pcf And_Gate_Project.blif -o And_Gate_Project.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif And_Gate_Project.blif...
prune...
read_pcf And_Gate_Project.pcf...
instantiate_io...
pack...

After packing:
IOs          3 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          1 / 1280
  DFF        0
  CARRY      0
  CARRY, DFF 0
  DFF PASS   0
  CARRY PASS 0
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted 0 nets
  0 globals
realize_constants...
place...
  initial wire length = 46
  at iteration #50: temp = 9.21117, wire length = 21
  at iteration #100: temp = 2.56117, wire length = 7
  final wire length = 6

After placement:
PIOs       3 / 72
PLBs       1 / 160
BRAMs      0 / 16

  place time 0.00s
route...
  pass 1, 0 shared.

After routing:
span_4     2 / 6944
span_12    0 / 1440

  route time 0.01s
write_txt And_Gate_Project.asc...

convert to binary

[tingo@localhost project_2]$ icepack And_Gate_Project.asc And_Gate_Project.bin

program

[tingo@localhost project_2]$ sudo /usr/local/bin/iceprog And_Gate_Project.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

and it works.

2017-04-04: test - see if I can program the initial image:

[tingo@localhost fpga_image]$ sudo /usr/local/bin/iceprog Go_Board_Full_Test_bitmap.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32300
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.
[tingo@localhost fpga_image]$ pwd
/home/tingo/doc/Nandland/Go_board/fpga_image

I can, and it works.

2017-04-04: project 1 - summary: first, the open source toolchain works. Nice. It supports Verilog. Second: you need a constraints file, but you only need to define constraints for the resources you have used in your design.

2017-04-04: try to program with iceprog:

[tingo@localhost 0_lessons]$ sudo /usr/local/bin/iceprog Switches_To_LEDs.bin
init..
cdone: high
reset..
cdone: low
flash ID: 0x20 0x20 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
file size: 32220
erase 64kB sector at 0x000000..
programming..
reading..
VERIFY OK
cdone: high
Bye.

does it work? Yes, it does!

2017-04-04: lsusb shows this for the Go board:

[tingo@localhost nandland_go]$ lsusb -d 0403:6010
Bus 001 Device 006: ID 0403:6010 Future Technology Devices International, Ltd FT2232C Dual USB-UART/FIFO IC

perhaps it will just work with iceprog?

2017-04-03: The Go board shows up as two usb serial ports when connected:

[tingo@localhost ~]$ ls -l /dev/ttyU*
crw-rw----. 1 root dialout 188, 0 Apr  3 16:37 /dev/ttyUSB0
crw-rw----. 1 root dialout 188, 1 Apr  3 16:37 /dev/ttyUSB1

ok.

2017-04-03: convert to binary format

[tingo@localhost 0_lessons]$ icepack Switches_To_LEDs.asc Switches_To_LEDs.bin
[tingo@localhost 0_lessons]$ ls -lh Switches_To_LEDs.asc Switches_To_LEDs.bin
-rw-rw-r--. 1 tingo tingo 180K Apr  3 16:31 Switches_To_LEDs.asc
-rw-rw-r--. 1 tingo tingo  32K Apr  3 16:34 Switches_To_LEDs.bin

ok

2017-04-03: place-and-route with arachne-pnr

[tingo@localhost 0_lessons]$ arachne-pnr -d 1k -P vq100 -p Switches_To_LEDs.pcf Switches_To_LEDs.blif -o Switches_To_LEDs.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif Switches_To_LEDs.blif...
prune...
read_pcf Switches_To_LEDs.pcf...
fatal error: read_pcf: failed to open `Switches_To_LEDs.pcf': No such file or directory

ok, let me try without the PCF, runs forever. The PCF is a constraints file, you really need one.

[tingo@localhost 0_lessons]$ arachne-pnr -d 1k -P vq100 -p Go_Board_Constraints.pcf Switches_To_LEDs.blif -o Switches_To_LEDs.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif Switches_To_LEDs.blif...
prune...
read_pcf Go_Board_Constraints.pcf...
Go_Board_Constraints.pcf:16: fatal error: no port `i_Clk' in top-level module `Switches_To_LEDs'

do I really need to define the FPGA clock? I try with a PCF file where I just remove everything I don't (think I) need

[tingo@localhost 0_lessons]$ arachne-pnr -d 1k -P vq100 -p Switches_To_LEDs.pcf Switches_To_LEDs.blif -o Switches_To_LEDs.asc
seed: 1
device: 1k
read_chipdb +/share/arachne-pnr/chipdb-1k.bin...
  supported packages: cb121, cb132, cb81, cm121, cm36, cm49, cm81, qn84, swg16tr, tq144, vq100
read_blif Switches_To_LEDs.blif...
prune...
read_pcf Switches_To_LEDs.pcf...
instantiate_io...
pack...

After packing:
IOs          8 / 72
GBs          0 / 8
  GB_IOs     0 / 8
LCs          0 / 1280
  DFF        0
  CARRY      0
  CARRY, DFF 0
  DFF PASS   0
  CARRY PASS 0
BRAMs        0 / 16
WARMBOOTs    0 / 1
PLLs         0 / 1

place_constraints...
promote_globals...
  promoted 0 nets
  0 globals
realize_constants...
place...
  initial wire length = 11
  at iteration #50: temp = 7.92282, wire length = 11
  final wire length = 11

After placement:
PIOs       5 / 72
PLBs       0 / 160
BRAMs      0 / 16

  place time 0.00s
route...
  pass 1, 0 shared.

After routing:
span_4     6 / 6944
span_12    0 / 1440

  route time 0.01s
write_txt Switches_To_LEDs.asc...

well, it finished at least.

2017-04-03: synthesize first example with Yosys

[tingo@localhost 0_lessons]$ yosys -p "synth_ice40 -blif Switches_To_LEDs.blif" Switches_To_LEDs.v

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2016  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)


-- Parsing `Switches_To_LEDs.v' using frontend `verilog' --

1. Executing Verilog-2005 frontend.
Parsing Verilog input from `Switches_To_LEDs.v' to AST representation.
Generating RTLIL representation for module `\Switches_To_LEDs'.
Successfully finished Verilog frontend.

-- Running command `synth_ice40 -blif Switches_To_LEDs.blif' --

2. Executing SYNTH_ICE40 pass.

2.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Successfully finished Verilog frontend.

2.2. Executing HIERARCHY pass (managing design hierarchy).

2.2.1. Finding top of design hierarchy..
root of   0 design levels: Switches_To_LEDs    
Automatically selected Switches_To_LEDs as design top module.

2.2.2. Analyzing design hierarchy..
Top module:  \Switches_To_LEDs

2.2.3. Analyzing design hierarchy..
Top module:  \Switches_To_LEDs
Removed 0 unused modules.

2.3. Executing PROC pass (convert processes to netlists).

2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3.3. Executing PROC_INIT pass (extract init attributes).

2.3.4. Executing PROC_ARST pass (detect async resets in processes).

2.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.3.6. Executing PROC_DLATCH pass (convert process syncs to latches).

2.3.7. Executing PROC_DFF pass (convert process syncs to FFs).

2.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.4. Executing FLATTEN pass (flatten design).
No more expansions possible.

2.5. Executing TRIBUF pass.

2.6. Executing DEMINOUT pass (demote inout ports to input or output).

2.7. Executing SYNTH pass.

2.7.1. Executing PROC pass (convert processes to netlists).

2.7.1.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.7.1.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.7.1.3. Executing PROC_INIT pass (extract init attributes).

2.7.1.4. Executing PROC_ARST pass (detect async resets in processes).

2.7.1.5. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.7.1.6. Executing PROC_DLATCH pass (convert process syncs to latches).

2.7.1.7. Executing PROC_DFF pass (convert process syncs to FFs).

2.7.1.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.7.2. Executing OPT_EXPR pass (perform const folding).

2.7.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.7.4. Executing CHECK pass (checking for obvious problems).
checking module Switches_To_LEDs..
found and reported 0 problems.

2.7.5. Executing OPT pass (performing simple optimizations).

2.7.5.1. Executing OPT_EXPR pass (perform const folding).

2.7.5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Switches_To_LEDs'.
Removed a total of 0 cells.

2.7.5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Switches_To_LEDs..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.7.5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \Switches_To_LEDs.
Performed a total of 0 changes.

2.7.5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Switches_To_LEDs'.
Removed a total of 0 cells.

2.7.5.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.7.5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.7.5.8. Executing OPT_EXPR pass (perform const folding).

2.7.5.9. Finished OPT passes. (There is nothing left to do.)

2.7.6. Executing WREDUCE pass (reducing word size of cells).

2.7.7. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module Switches_To_LEDs:
  created 0 $alu and 0 $macc cells.

2.7.8. Executing SHARE pass (SAT-based resource sharing).

2.7.9. Executing OPT pass (performing simple optimizations).

2.7.9.1. Executing OPT_EXPR pass (perform const folding).

2.7.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Switches_To_LEDs'.
Removed a total of 0 cells.

2.7.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Switches_To_LEDs..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.7.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \Switches_To_LEDs.
Performed a total of 0 changes.

2.7.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Switches_To_LEDs'.
Removed a total of 0 cells.

2.7.9.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.7.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.7.9.8. Executing OPT_EXPR pass (perform const folding).

2.7.9.9. Finished OPT passes. (There is nothing left to do.)

2.7.10. Executing FSM pass (extract and optimize FSM).

2.7.10.1. Executing FSM_DETECT pass (finding FSMs in design).

2.7.10.2. Executing FSM_EXTRACT pass (extracting FSM from design).

2.7.10.3. Executing FSM_OPT pass (simple optimizations of FSMs).

2.7.10.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.7.10.5. Executing FSM_OPT pass (simple optimizations of FSMs).

2.7.10.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

2.7.10.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

2.7.10.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

2.7.11. Executing OPT pass (performing simple optimizations).

2.7.11.1. Executing OPT_EXPR pass (perform const folding).

2.7.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Switches_To_LEDs'.
Removed a total of 0 cells.

2.7.11.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.7.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.7.11.5. Finished fast OPT passes.

2.7.12. Executing MEMORY pass.

2.7.12.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).

2.7.12.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.7.12.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

2.7.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.7.12.5. Executing MEMORY_COLLECT pass (generating $mem cells).

2.7.13. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.8. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).

2.9. Executing TECHMAP pass (map to technology primitives).

2.9.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
Successfully finished Verilog frontend.
No more expansions possible.

2.10. Executing OPT pass (performing simple optimizations).

2.10.1. Executing OPT_EXPR pass (perform const folding).

2.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Switches_To_LEDs'.
Removed a total of 0 cells.

2.10.3. Executing OPT_RMDFF pass (remove dff with constant values).

2.10.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.10.5. Finished fast OPT passes.

2.11. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).

2.12. Executing OPT pass (performing simple optimizations).

2.12.1. Executing OPT_EXPR pass (perform const folding).

2.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Switches_To_LEDs'.
Removed a total of 0 cells.

2.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \Switches_To_LEDs..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \Switches_To_LEDs.
Performed a total of 0 changes.

2.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Switches_To_LEDs'.
Removed a total of 0 cells.

2.12.6. Executing OPT_RMDFF pass (remove dff with constant values).

2.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.12.8. Executing OPT_EXPR pass (perform const folding).

2.12.9. Finished OPT passes. (There is nothing left to do.)

2.13. Executing TECHMAP pass (map to technology primitives).

2.13.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

2.13.2. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.
No more expansions possible.

2.14. Executing ICE40_OPT pass (performing simple optimizations).

2.14.1. Running ICE40 specific optimizations.

2.14.2. Executing OPT_EXPR pass (perform const folding).

2.14.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Switches_To_LEDs'.
Removed a total of 0 cells.

2.14.4. Executing OPT_RMDFF pass (remove dff with constant values).

2.14.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.14.6. Finished OPT passes. (There is nothing left to do.)

2.15. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).

2.16. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
Selected cell types for direct conversion:
  $_DFF_PP1_ -> $__DFFE_PP1
  $_DFF_PP0_ -> $__DFFE_PP0
  $_DFF_PN1_ -> $__DFFE_PN1
  $_DFF_PN0_ -> $__DFFE_PN0
  $_DFF_NP1_ -> $__DFFE_NP1
  $_DFF_NP0_ -> $__DFFE_NP0
  $_DFF_NN1_ -> $__DFFE_NN1
  $_DFF_NN0_ -> $__DFFE_NN0
  $_DFF_N_ -> $_DFFE_NP_
  $_DFF_P_ -> $_DFFE_PP_
Transforming FF to FF+Enable cells in module Switches_To_LEDs:

2.17. Executing TECHMAP pass (map to technology primitives).

2.17.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
No more expansions possible.

2.18. Executing OPT_EXPR pass (perform const folding).

2.19. Executing SIMPLEMAP pass (map simple cells to gate primitives).

2.20. Executing ICE40_FFINIT pass (implement FF init values).
Handling FF init values in Switches_To_LEDs.

2.21. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).
Merging set/reset $_MUX_ cells into SB_FFs in Switches_To_LEDs.

2.22. Executing ICE40_OPT pass (performing simple optimizations).

2.22.1. Running ICE40 specific optimizations.

2.22.2. Executing OPT_EXPR pass (perform const folding).

2.22.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\Switches_To_LEDs'.
Removed a total of 0 cells.

2.22.4. Executing OPT_RMDFF pass (remove dff with constant values).

2.22.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \Switches_To_LEDs..

2.22.6. Finished OPT passes. (There is nothing left to do.)

2.23. Executing TECHMAP pass (map to technology primitives).

2.23.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.
No more expansions possible.

2.24. Executing ABC pass (technology mapping using ABC).

2.24.1. Extracting gate netlist of module `\Switches_To_LEDs' to `<abc-temp-dir>/input.blif'..
Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

2.25. Executing TECHMAP pass (map to technology primitives).

2.25.1. Executing Verilog-2005 frontend.
Parsing Verilog input from `/usr/local/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
No more expansions possible.

2.26. Executing HIERARCHY pass (managing design hierarchy).

2.26.1. Analyzing design hierarchy..
Top module:  \Switches_To_LEDs

2.26.2. Analyzing design hierarchy..
Top module:  \Switches_To_LEDs
Removed 0 unused modules.

2.27. Printing statistics.

=== Switches_To_LEDs ===

   Number of wires:                  8
   Number of wire bits:              8
   Number of public wires:           8
   Number of public wire bits:       8
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  0

2.28. Executing CHECK pass (checking for obvious problems).
checking module Switches_To_LEDs..
found and reported 0 problems.

2.29. Executing BLIF backend.

End of script. Logfile hash: 4437af27a1
CPU: user 0.20s system 0.02s, MEM: 41.18 MB total, 10.97 MB resident
Yosys 0.7+161 (git sha1 58ee8e3, clang 3.8.1 -fPIC -Os)
Time spent: 60% 9x read_verilog (0 sec), 14% 1x share (0 sec), ...

ok.

2017-04-03: first example

[tingo@localhost 0_lessons]$ cat Switches_To_LEDs.v
module Switches_To_LEDs
  (input i_Switch_1,  
   input i_Switch_2,
   input i_Switch_3,
   input i_Switch_4,
   output o_LED_1,
   output o_LED_2,
   output o_LED_3,
   output o_LED_4);

assign o_LED_1 = i_Switch_1;
assign o_LED_2 = i_Switch_2;
assign o_LED_3 = i_Switch_3;
assign o_LED_4 = i_Switch_4;

endmodule

ok.

2017-04-03: IceStorm - compile and install Icestorm Tools

[tingo@localhost nandland_go]$ cd icestorm
[tingo@localhost icestorm]$ make -j4
for dir in icebox icepack iceprog icemulti icepll icetime icebram; do \
 make -C $dir all || exit; \
done
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icebox'
python3 icebox_chipdb.py -3 > chipdb-384.new
python3 icebox_chipdb.py > chipdb-1k.new
python3 icebox_chipdb.py -8 > chipdb-8k.new
mv chipdb-384.new chipdb-384.txt
mv chipdb-1k.new chipdb-1k.txt
mv chipdb-8k.new chipdb-8k.txt
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icebox'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icepack'
g++ -MD -O0 -ggdb -Wall -std=c++11 -I/usr/local/include   -c -o icepack.o icepack.cc
g++ -o icepack  icepack.o -lm -lstdc++
ln -sf icepack iceunpack
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icepack'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/iceprog'
cc -MD -O0 -ggdb -Wall -std=c99 -I/usr/local/include -I/usr/include/libftdi1 -I/usr/include/libusb-1.0   -c -o iceprog.o iceprog.c
cc -o iceprog  iceprog.o -L/usr/local/lib -lm -lftdi1 -lusb-1.0
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/iceprog'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icemulti'
g++ -MD -O0 -ggdb -Wall -std=c++11 -I/usr/local/include   -c -o icemulti.o icemulti.cc
g++ -o icemulti  icemulti.o -lm -lstdc++
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icemulti'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icepll'
g++ -MD -O0 -ggdb -Wall -std=c++11 -I/usr/local/include   -c -o icepll.o icepll.cc
g++ -o icepll  icepll.o -lm -lstdc++
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icepll'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icetime'
python3 timings.py > timings.inc.new
mv timings.inc.new timings.inc
g++ -MD -O0 -ggdb -Wall -std=c++11 -I/usr/local/include -DPREFIX='"/usr/local"' -DCHIPDB_SUBDIR='"icebox"'   -c -o icetime.o icetime.cc
g++ -o icetime  icetime.o -lm -lstdc++
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icetime'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icebram'
g++ -MD -O0 -ggdb -Wall -std=c++11 -I/usr/local/include   -c -o icebram.o icebram.cc
g++ -o icebram  icebram.o -lm -lstdc++
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icebram'
install
[tingo@localhost icestorm]$ sudo make install
for dir in icebox icepack iceprog icemulti icepll icetime icebram; do \
 make -C $dir install || exit; \
done
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icebox'
mkdir -p /usr/local/share/icebox
mkdir -p /usr/local/bin
cp chipdb-384.txt    /usr/local/share/icebox/
cp chipdb-1k.txt     /usr/local/share/icebox/
cp chipdb-8k.txt     /usr/local/share/icebox/
cp icebox.py         /usr/local/bin/icebox.py
cp iceboxdb.py       /usr/local/bin/iceboxdb.py
cp icebox_chipdb.py  /usr/local/bin/icebox_chipdb
cp icebox_diff.py    /usr/local/bin/icebox_diff
cp icebox_explain.py /usr/local/bin/icebox_explain
cp icebox_colbuf.py  /usr/local/bin/icebox_colbuf
cp icebox_html.py    /usr/local/bin/icebox_html
cp icebox_maps.py    /usr/local/bin/icebox_maps
cp icebox_vlog.py    /usr/local/bin/icebox_vlog
cp icebox_stat.py    /usr/local/bin/icebox_stat
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icebox'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icepack'
mkdir -p /usr/local/bin
cp icepack /usr/local/bin/icepack
ln -sf icepack /usr/local/bin/iceunpack
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icepack'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/iceprog'
mkdir -p /usr/local/bin
cp iceprog /usr/local/bin/iceprog
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/iceprog'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icemulti'
mkdir -p /usr/local/bin
cp icemulti /usr/local/bin/icemulti
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icemulti'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icepll'
mkdir -p /usr/local/bin
cp icepll /usr/local/bin/icepll
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icepll'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icetime'
mkdir -p /usr/local/bin
cp icetime /usr/local/bin/icetime
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icetime'
make[1]: Entering directory '/home/tingo/work/nandland_go/icestorm/icebram'
mkdir -p /usr/local/bin
cp icebram /usr/local/bin/icebram
make[1]: Leaving directory '/home/tingo/work/nandland_go/icestorm/icebram'

Arachne-PNR

[tingo@localhost icestorm]$ cd ..
[tingo@localhost nandland_go]$ cd arachne-pnr
[tingo@localhost arachne-pnr]$ make -j4
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/arachne-pnr.o src/arachne-pnr.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/netlist.o src/netlist.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/blif.o src/blif.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/pack.o src/pack.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/place.o src/place.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/util.o src/util.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/io.o src/io.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/route.o src/route.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/chipdb.o src/chipdb.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/location.o src/location.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/configuration.o src/configuration.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/line_parser.o src/line_parser.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/pcf.o src/pcf.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/global.o src/global.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/constant.o src/constant.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/designstate.o src/designstate.cc
echo "const char *version_str = \"arachne-pnr 0.1+191+0 (git sha1 e83eecb, g++ `g++ --version | tr ' ()' '\n' | grep '^[0-9]' | head -n1` -O2)\";" > src/version_16822.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror   -c -o src/version_16822.o src/version_16822.cc
g++ -Isrc -std=c++11 -MD -O2 -Wall -Wshadow -Wsign-compare -Werror  -o bin/arachne-pnr src/arachne-pnr.o src/netlist.o src/blif.o src/pack.o src/place.o src/util.o src/io.o src/route.o src/chipdb.o src/location.o src/configuration.o src/line_parser.o src/pcf.o src/global.o src/constant.o src/designstate.o src/version_16822.o -lm
mkdir -p share/arachne-pnr
mkdir -p share/arachne-pnr
mkdir -p share/arachne-pnr
bin/arachne-pnr -d 384 -c /usr/local/share/icebox/chipdb-384.txt --write-binary-chipdb share/arachne-pnr/chipdb-384.bin
bin/arachne-pnr -d 1k -c /usr/local/share/icebox/chipdb-1k.txt --write-binary-chipdb share/arachne-pnr/chipdb-1k.bin
bin/arachne-pnr -d 8k -c /usr/local/share/icebox/chipdb-8k.txt --write-binary-chipdb share/arachne-pnr/chipdb-8k.bin
seed: 1
device: 384
read_chipdb /usr/local/share/icebox/chipdb-384.txt...
seed: 1
device: 8k
read_chipdb /usr/local/share/icebox/chipdb-8k.txt...
seed: 1
device: 1k
read_chipdb /usr/local/share/icebox/chipdb-1k.txt...
write_binary_chipdb share/arachne-pnr/chipdb-384.bin
write_binary_chipdb share/arachne-pnr/chipdb-1k.bin
write_binary_chipdb share/arachne-pnr/chipdb-8k.bin

install

[tingo@localhost arachne-pnr]$ sudo make install
mkdir -p /usr/local/bin
cp bin/arachne-pnr /usr/local/bin/arachne-pnr
mkdir -p /usr/local/share/arachne-pnr
cp share/arachne-pnr/chipdb-384.bin /usr/local/share/arachne-pnr/chipdb-384.bin
cp share/arachne-pnr/chipdb-1k.bin /usr/local/share/arachne-pnr/chipdb-1k.bin
cp share/arachne-pnr/chipdb-8k.bin /usr/local/share/arachne-pnr/chipdb-8k.bin

Yosys

[tingo@localhost arachne-pnr]$ cd ..
[tingo@localhost nandland_go]$ cd yosys
[tingo@localhost yosys]$ make -j4
[...]
[100%] Building yosys-abc

  Build successful.

install

[tingo@localhost yosys]$ sudo make install
mkdir -p /usr/local/bin
install yosys yosys-config yosys-abc yosys-filterlib yosys-smtbmc /usr/local/bin
mkdir -p /usr/local/share/yosys
cp -r share/. /usr/local/share/yosys/.

ok.

2017-04-03: IceStorm - get the source IceStorm Tools

[tingo@localhost nandland_go]$ pwd
/home/tingo/work/nandland_go
[tingo@localhost nandland_go]$ git clone https://github.com/cliffordwolf/icestorm.git icestorm
Cloning into 'icestorm'...
remote: Counting objects: 1913, done.
remote: Total 1913 (delta 0), reused 0 (delta 0), pack-reused 1913
Receiving objects: 100% (1913/1913), 933.03 KiB | 327.00 KiB/s, done.
Resolving deltas: 100% (1228/1228), done.
Checking connectivity... done.

Arachne-PNR

[tingo@localhost nandland_go]$ git clone https://github.com/cseed/arachne-pnr.git arachne-pnr
Cloning into 'arachne-pnr'...
remote: Counting objects: 1427, done.
remote: Compressing objects: 100% (4/4), done.
remote: Total 1427 (delta 0), reused 0 (delta 0), pack-reused 1423
Receiving objects: 100% (1427/1427), 475.48 KiB | 195.00 KiB/s, done.
Resolving deltas: 100% (998/998), done.
Checking connectivity... done.

Yosys

[tingo@localhost nandland_go]$ git clone https://github.com/cliffordwolf/yosys.git yosys
Cloning into 'yosys'...
remote: Counting objects: 21773, done.
remote: Compressing objects: 100% (36/36), done.
remote: Total 21773 (delta 14), reused 0 (delta 0), pack-reused 21737
Receiving objects: 100% (21773/21773), 6.84 MiB | 331.00 KiB/s, done.
Resolving deltas: 100% (15199/15199), done.
Checking connectivity... done.

ok.

2017-04-03: IceStorm - install prerequisites.

[tingo@localhost ~]$ sudo dnf install make automake gcc gcc-c++ kernel-devel clang bison flex readline-devel gawk tcl-devel libffi-devel git mercurial graphviz python-xdot pkgconfig python python3 libftdi-devel
[sudo] password for tingo: 
Last metadata expiration check: 0:37:04 ago on Mon Apr  3 14:15:04 2017.
Package make-1:4.1-5.fc24.x86_64 is already installed, skipping.
Package gcc-6.3.1-1.fc24.x86_64 is already installed, skipping.
Package gawk-4.1.3-8.fc24.x86_64 is already installed, skipping.
Package git-2.7.4-3.fc24.x86_64 is already installed, skipping.
Package pkgconfig-1:0.29-2.fc24.x86_64 is already installed, skipping.
Package python-2.7.13-1.fc24.x86_64 is already installed, skipping.
Package python3-3.5.2-3.fc24.x86_64 is already installed, skipping.
Dependencies resolved.
=====================================================================================================================================
 Package                            Arch                   Version                                     Repository               Size
=====================================================================================================================================
Installing:
 autoconf                           noarch                 2.69-22.fc24                                fedora                  709 k
 automake                           noarch                 1.15-6.fc24                                 fedora                  695 k
 bison                              x86_64                 3.0.4-4.fc24                                fedora                  684 k
 clang                              x86_64                 3.8.1-1.fc24                                updates                 311 k
 clang-libs                         x86_64                 3.8.1-1.fc24                                updates                 8.2 M
 compiler-rt                        x86_64                 3.8.1-1.fc24                                updates                 1.2 M
 flex                               x86_64                 2.6.0-3.fc24                                updates                 314 k
 gcc-c++                            x86_64                 6.3.1-1.fc24                                updates                  11 M
 graphviz                           x86_64                 2.38.0-33.fc24                              fedora                  3.2 M
 gts                                x86_64                 0.7.6-29.20121130.fc24                      fedora                  226 k
 kernel-devel                       x86_64                 4.10.6-100.fc24                             updates                  11 M
 lasi                               x86_64                 1.1.2-6.fc24                                fedora                   46 k
 libconfuse                         x86_64                 2.7-10.fc24                                 fedora                   83 k
 libffi-devel                       x86_64                 3.1-9.fc24                                  fedora                   27 k
 libftdi-devel                      x86_64                 1.2-8.fc24                                  fedora                  283 k
 libstdc++-devel                    x86_64                 6.3.1-1.fc24                                updates                 1.8 M
 libusbx-devel                      x86_64                 1.0.21-0.1.git448584a.fc24                  fedora                   27 k
 mercurial                          x86_64                 3.7.3-1.fc24                                fedora                  3.3 M
 ncurses-c++-libs                   x86_64                 6.0-6.20160709.fc24                         updates                  54 k
 ncurses-devel                      x86_64                 6.0-6.20160709.fc24                         updates                 504 k
 netpbm                             x86_64                 10.77.00-3.fc24                             updates                 197 k
 perl-Thread-Queue                  noarch                 3.12-1.fc24                                 updates                  22 k
 python-xdot                        noarch                 0.6-4.fc24                                  fedora                   55 k
 readline-devel                     x86_64                 6.3-8.fc24                                  fedora                  179 k
 tcl-devel                          x86_64                 1:8.6.5-1.fc24                              fedora                  187 k
Skipping packages with conflicts:
(add '--best --allowerasing' to command line to force their upgrade):
 python3                            x86_64                 3.5.3-3.fc24                                updates                  57 k
 python3-libs                       x86_64                 3.5.3-3.fc24                                updates                 1.4 M
 system-python                      x86_64                 3.5.3-3.fc24                                updates                  51 k
 system-python-libs                 x86_64                 3.5.3-3.fc24                                updates                 6.3 M

Transaction Summary
=====================================================================================================================================
Install  25 Packages
Skip      4 Packages

Total download size: 44 M
Installed size: 213 M
Is this ok [y/N]: y
[...]
Installed:
  autoconf.noarch 2.69-22.fc24                  automake.noarch 1.15-6.fc24                       bison.x86_64 3.0.4-4.fc24         
  clang.x86_64 3.8.1-1.fc24                     clang-libs.x86_64 3.8.1-1.fc24                    compiler-rt.x86_64 3.8.1-1.fc24   
  flex.x86_64 2.6.0-3.fc24                      gcc-c++.x86_64 6.3.1-1.fc24                       graphviz.x86_64 2.38.0-33.fc24    
  gts.x86_64 0.7.6-29.20121130.fc24             kernel-devel.x86_64 4.10.6-100.fc24               lasi.x86_64 1.1.2-6.fc24          
  libconfuse.x86_64 2.7-10.fc24                 libffi-devel.x86_64 3.1-9.fc24                    libftdi-devel.x86_64 1.2-8.fc24   
  libstdc++-devel.x86_64 6.3.1-1.fc24           libusbx-devel.x86_64 1.0.21-0.1.git448584a.fc24   mercurial.x86_64 3.7.3-1.fc24     
  ncurses-c++-libs.x86_64 6.0-6.20160709.fc24   ncurses-devel.x86_64 6.0-6.20160709.fc24          netpbm.x86_64 10.77.00-3.fc24     
  perl-Thread-Queue.noarch 3.12-1.fc24          python-xdot.noarch 0.6-4.fc24                     readline-devel.x86_64 6.3-8.fc24  
  tcl-devel.x86_64 1:8.6.5-1.fc24              

Complete!

ok.

2017-04-03: installing iCEcube2 - setup fails:

[tingo@localhost Lattice]$ ./iCEcube2setup_Jan_13_2017_1701
bash: ./iCEcube2setup_Jan_13_2017_1701: /lib/ld-linux.so.2: bad ELF interpreter: No such file or directory

hmm..

[tingo@localhost Lattice]$ ldd iCEcube2setup_Jan_13_2017_1701
 not a dynamic executable

ok.

[tingo@localhost Lattice]$ file iCEcube2setup_Jan_13_2017_1701
iCEcube2setup_Jan_13_2017_1701: ELF 32-bit LSB executable, Intel 80386, version 1 (SYSV), dynamically linked, interpreter /lib/ld-linux.so.2, for GNU/Linux 2.2.5, not stripped

or not ok? aha, it seems this program is 32-bit only. Oh well.

2017-04-03: registered an account at latticesemi, downloaded IceCube2, requested and got a license. Downloaded Diamond Programmer

2017-04-03: I'm using my Fedora laptop:

[tingo@localhost ~]$ lsb_release -a
LSB Version: :core-4.1-amd64:core-4.1-noarch:cxx-4.1-amd64:cxx-4.1-noarch:desktop-4.1-amd64:desktop-4.1-noarch:languages-4.1-amd64:languages-4.1-noarch:printing-4.1-amd64:printing-4.1-noarch
Distributor ID: Fedora
Description: Fedora release 24 (Twenty Four)
Release: 24
Codename: TwentyFour
[tingo@localhost ~]$ uname -a
Linux localhost.localdomain 4.9.10-100.fc24.x86_64 #1 SMP Wed Feb 15 18:35:50 UTC 2017 x86_64 x86_64 x86_64 GNU/Linux

ok.

2017-04-03: testing the Go board. I connected the board to my workstation with a usb - micro usb cable. The power LED turned on. Pressing the four buttons lit up four other LEDs, as well as the seven segment displays. My workstation runs:

tingo@kg-core1$ uname -a
FreeBSD kg-core1.kg4.no 10.3-STABLE FreeBSD 10.3-STABLE #0 r310083: Wed Dec 14 21:00:13 CET 2016     root@kg-core1.kg4.no:/usr/obj/usr/src/sys/GENERIC  amd64

and the board shows up in /var/log/messages as

Apr  3 10:20:49 kg-core1 kernel: ugen3.6: <FTDI> at usbus3
Apr  3 10:20:49 kg-core1 kernel: uftdi0: <Dual RS232-HS> on usbus3
Apr  3 10:20:49 kg-core1 kernel: uftdi1: <Dual RS232-HS> on usbus3

nice.

2016-04-07: unpacking - the package contains just the Go board in an antistatic bubble bag and a small laminated card directing to Nandland web site and Youtube channel.

2016-04-07: I received a pick-up letter in my physical mailbox, and discovered the Posten (the postal service) had changed tracking number on the package - not nice!. After work, I went to my local PIB (Coop Extra Trondheimsveien) paid NOK 252.- (value added tax: NOK 106.- + handling fee NOK 146.-) and got the package. Details of this tracking number:

Hendelse    Tid     Sted
Sendingen er ankommet Extra Trondheimsveien
Siste hentedato: 20.04.2016
Hentekode: RH89
    06.04.2016 14:40    0506 OSLO  
Sendingen er ankommet terminal og blir videresendt
    06.04.2016 07:49    0024 OSLO  
Sendingen er tollbehandlet og sendes til mottaker.
    06.04.2016 07:18    0024 OSLO  

annoying break in tracking, due to the change of tracking number.

2016-04-05: tracking - at 08:27 local time the package has been through Customs, and has been forwarded. Tracking details:

Hendelse    Tid     Sted
Sendingen er ankommet terminal og blir videresendt
    05.04.2016 08:27    0074 OSLO  
Sendingen er under importbehandling
    05.04.2016 08:27    0074 OSLO  
Sendingen er sortert og videresendt
    01.04.2016 19:23    1470 LØRENSKOG  
Sendingen er ankommet mottakerlandet
    01.04.2016 13:54    OSLO LETTER CENTER  

2016-04-01: tracking - the package has arrived in my country (no, not an April Fools joke)

2016-03-29: I got a "shipped" notice via email from VIPparcel, with a tracking number.

2016-01-23: I responded to the project survey.

2015-12-25: the project was funded.

2015-11-28: I backed the Nandland GO Board with USD 70.- (60 + 10 shipping) with a reward of "Receive a fully assembled and tested Go Board. Micro USB Cable not included.", estimated delivery Feb 2016.