ULX3S - FreeBSD
back to ulx3s page.
links
Github ulx3s, ulx3s/quick-start, ulx3s/blink, fujprog, open-tool-forge/fpga-toolchain, ldoolitt/vhd2vl,
more links
YosysHQ: yosys-plugins, Oberon - Project Oberon, Project Oberon / Linux, Oberon-extended, github.com/Spirit-of-Oberon, Tech Note 002 - Adjusting Module, Stack, Heap, and Video Memory, Video Timings Calculator, VGA Signal timing, Display Industry standard archive, OSDev wiki Video Signals and Timing,
examples
Github emard/icy99, emard/oberon, emard/ulx3s-misc, emard/ulx3s_trs_80, emard/ulx3s_zx_spectrum, emard/ulx3s_zx81, Gitlab pnru/ti99_2, pnru/ulx3s-misc,
more examples
lawrie/jupiter_ace, lawrie/ulx3s_bit_streams, lawrie/ulx3s_cpm_z80, dan-rodrigues/icestation-32,
code: emard/ulx3s-misc - check dvi, ecp5pll,
local links
c2 - FreeBSD workstation,
History
2020-11-29: c2 - ada0p5 - tested the dan-rodrigues/icestation-32 example on my 85F board. Works nicely. No sound connected, so I can't say anything about that. The initial .bit file prints out "WINBOND", so my board has a winbond flash chip. Had to make small changes - g++ -> g++9, python3 -> python3.8. Software uploading via the bash script works nicely
tingo@kg-core2$ pwd /home/tingo/doc/Radiona/ULX3S/examples/dan-rodrigues/icestation-32/software/sprites tingo@kg-core2$ bash ../../scripts/run prog.bin Running prog.bin (65540)... Replacing BRAM data... Running ecppack... Uploading to SRAM through fujprog... ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Using USB cable: ULX3S FPGA 85K v3.0.8 Programming: 100% Completed in 9.88 seconds. Completed, cleaning up.
ok. The riscv toolchain I use is here:
tingo@kg-core2$ ll ~/dl/lin/xpack-riscv-none-embed-gcc-8.3.0-1.1-linux-x64.tgz -rw-r--r-- 1 tingo tingo - 318196117 Nov 29 21:20 /home/tingo/dl/lin/xpack-riscv-none-embed-gcc-8.3.0-1.1-linux-x64.tgz
installed
tingo@kg-core2$ l ~/progs/xPacks/riscv-none-embed-gcc/8.3.0-1.1/bin/ ./ libz.so.1.2.8 riscv-none-embed-gcov-tool* ../ riscv-none-embed-addr2line* riscv-none-embed-gdb* libexpat.so.1@ riscv-none-embed-ar* riscv-none-embed-gdb-add-index* libexpat.so.1.6.7 riscv-none-embed-as* riscv-none-embed-gdb-add-index-py* libfl.so.2@ riscv-none-embed-c++* riscv-none-embed-gdb-py* libfl.so.2.0.0 riscv-none-embed-c++filt* riscv-none-embed-gprof* libgmp.so.10@ riscv-none-embed-cpp* riscv-none-embed-ld* libgmp.so.10.3.2 riscv-none-embed-elfedit* riscv-none-embed-ld.bfd* libiconv.so.2@ riscv-none-embed-g++* riscv-none-embed-nm* libiconv.so.2.6.0 riscv-none-embed-gcc* riscv-none-embed-objcopy* liblzma.so.5@ riscv-none-embed-gcc-8.3.0* riscv-none-embed-objdump* liblzma.so.5.2.3 riscv-none-embed-gcc-ar* riscv-none-embed-ranlib* libmpfr.so.4@ riscv-none-embed-gcc-nm* riscv-none-embed-readelf* libmpfr.so.4.1.6 riscv-none-embed-gcc-ranlib* riscv-none-embed-size* libpython2.7.so.1.0 riscv-none-embed-gcov* riscv-none-embed-strings* libz.so.1@ riscv-none-embed-gcov-dump* riscv-none-embed-strip*
and added to $PATH
tingo@kg-core2$ echo $PATH /home/tingo/progs/fpga-toolchain/bin:/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/sbin:/usr/local/bin:/home/tingo/bin:/home/tingo/.local/bin:/home/tingo/progs/xPacks/riscv-none-embed-gcc/8.3.0-1.1/bin
that's all.
2020-11-26: c2 - ada0p5 - try out the precompiled litex binary from litex-hub/linux-on-litex-vexriscv-prebuilt:
tingo@kg-core2$ pwd /home/tingo/doc/Radiona/ULX3S/examples/litex-hub/linux-on-litex-vexriscv-prebuilt tingo@kg-core2$ fujprog build/ulx3s/gateware/top.svf ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Using USB cable: ULX3S FPGA 12K v3.0.8 Found LFE5U-12F device, but the bitstream is for LFE5U-45F. Failed.
ahww, it is for a different size fpga.
2020-11-18: c2 - ada0p5 - test the ST7789 1.3 inch OLED display (SPI). Using my 12F board, I first tried emard/ulx3s-misc - examples/hex/lcd_st7789_hex/proj - build, and shows a hex display when F1 is pressed, PWR is reset, the other buttons show up on the display (if F1 is held down and one of the other buttons is pushed down).
examples/oled/proj/ulx3s_checkered_v - no display
examples/spi_display/proj/st7789_vga_vhdl - First you need to set en environment variable
tingo@kg-core2$ export GHDL_PREFIX=~/progs/fpga-toolchain/lib/ghdl/
after that the project builds, and shows a test picture on the LCD display
2020-11-14: c2 - ada0p5 - oberon_pnr - I tested the ledboot.img.zip image - it works, and links the LEDs as it should. In the process I discovered that three of the non-name 1G microSD cards (the ones I bought cheap on eBay or somewhere) don't work properly. Oh Well.
2020-11-13: c2 - ada0p5 - oberon_pnr - tested the prebuilt bit/obst_85F.bit on my 85F board. It shows a perfect Oberon startup picture on my monitor (1024x768 @ 60 Hz), but keyboard (US2) and mouse (US3) don't work. Leds D7 and D2 are lit, pressing reset (PWR) doesn't help. Switching mouse and keyboard don't help either. But the bitstream I built (pnru_oberon_85f_seed_25_21.01_MHz.bit) boots and works. Nice! building a bitstream (pnru_oberon_85f_20.64_MHz.bit) from nextpnr-ecp5 without --seed also gives working Oberon. Double nice!
2020-11-13: c2 - ada0p5 - built oberon_pnr from pnru/ulx3s-misc. Tested nextpnr-ecp5 without and with --seed from 1 - 30. Without --seed I get
$ nextpnr-ecp5 --85k --package CABGA381 --json sys.json --lpf ulx3s_v20.lpf --textcfg sys.cfg ERROR: Max frequency for clock '$glbnet$clk_25mhz$TRELLIS_IO_IN': 20.64 MHz (FAIL at 25.00 MHz) ERROR: Max frequency for clock '$glbnet$pix5clk': 288.52 MHz (FAIL at 325.10 MHz)
with --seed 25 I get
$ nextpnr-ecp5 --seed 25 --85k --package CABGA381 --json sys.json --lpf ulx3s_v20.lpf --textcfg sys.cfg ERROR: Max frequency for clock '$glbnet$clk_25mhz$TRELLIS_IO_IN': 21.01 MHz (FAIL at 25.00 MHz)
so I built a bitstream from that:
$ ecppack --compress sys.cfg pnru_oberon_85f.bit
hmm, better rename that to keep track
$ mv pnru_oberon_85f.bit pnru_oberon_85f_seed_25_21.01_MHz.bit
ok.
2020-11-13: c2 - ada0p5 - upgraded the toolchain:
tingo@kg-core2$ cat ~/progs/fpga-toolchain/VERSION nightly-20201112
ok
2020-10-18: c2 - ada0p5 - testing examples/dvi from emard/ulx3s-misc - my monitor is a Benq GL2450HM (1920x1080 native resolution) and I'm using the 85F board. build
$ gmake FPGA_SIZE=85
program
$ gmake FPGA_SIZE=85 UJPROG=fujprog prog
results
640x400 @50Hz - "Out of range" - adjusting with xadjustf or yadjustf doesn't help 640x400 @60Hz - ok 640x480 @50Hz - ok 640x480 @60Hz - ok 720x576 @50Hz - ok 720x576 @60Hz - "HDMI no signal detected" - adjusting with xadjustf or yadjustf doesn't help 800x480 @60Hz - "HDMI no signal detected" 800x600 @60Hz - ok 1024x768 @60Hz - "HDMI no signal detected" 1280x768 @60Hz - ok 1366x768 @60Hz - "HDMI no signal detected" 1280x1024 @60Hz - ok 1920x1080 @30Hz - "HDMI no signal detected" 1920x1080 @50Hz overclock 540MHz - fails with Generating RTLIL representation for module `$paramod\ecp5pll\in_hz=25000000\out0_hz=540000000\out1_hz=108000000'. ../ecp5pll/hdl/sv/ecp5pll.sv:186: ERROR: out0_hz tolerance exceeds out0_tol_hz. gmake: *** [../../scripts/trellis_main.mk:124: dvi.json] Error 1 1920x1200 @50Hz overclock 600MHz - "HDMI no signal detected"
more testing
800x480 @50Hz - ok 1024x768 @50Hz - ok 1366x768 @60Hz - ok
other sizes
720x400 @60Hz - ok 720x400 @50Hz - "Out of range"
ok
2020-10-18: c2 - ada0p5 - lawrie/ulx3s_cpm_z80 - build for 12F board with
$ gmake DEVICE=12k
then save the bistream
$ cp -pv bin/toplevel.bit cpm_12f_sd.bit
next, build for 85F (default)
$ gmake clean $ gmake
save bitstream
$ cp -pv bin/toplevel.bit cpm_85f_sd.bit
program
$ fujprog cpm_85f_sd.bit
and (when the right microSD card is in the slot) CP/M works. But only in 40 coloumn mode on the VGA and PS/2 console. Why is that? On the serial console, everything is good (80 cols):
A>type files.txt A: B: C: D: ---------------------------------------------------------------- 0 0_GAMES 0_OLDUTILS 0_NEWUTILS 1_BDS_TINY_C 1_MUMATHSIMP 1_F80M80BASIC 1_ROMS 2_APL 2_CROSSTALK 2_AZTEC_C_106D 2_ZSYSTEM 3_JANUS_ADA15 3_QTERM43 3_TPASCAL3 3_MICROPRO 4_MS_COBOL 4_CLINK 4_DXFORTH401 4_MULTIPLAN 5_PILOT 5_SUPERSFTUTIL 5_PLI14 5_DBASEII 6_SYSLIB 6_RCPM 6_ALGOLM 6_DWG_APPS 7_BBC BASIC 7_DDTZ SOURCES 7_SUPERCALC 8_MICROSHELL ----------------------------------------------------------------
ok. stat
A>c:stat A: R/W, Space: 4840k B: R/W, Space: 3896k C: R/W, Space: 4256k D: R/W, Space: 3120k
survey
A>d:survey *** System Survey (June 82) *** Drive A: 3336K bytes in 431 files with 4840K bytes remaining Drive B: 32K bytes in 368 files with 8160K bytes remaining Drive C: 32K bytes in 357 files with 8160K bytes remaining Drive D: 32K bytes in 383 files with 8160K bytes remaining Memory map: 0 8 16 24 32 40 48 56 64 | | | | | | | | | TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTCCCBBBBBBB T=TPA C=CPM B=BIOS or unassigned R=ROM or bad BIOS at E603 iobyte 01 drive 00 BDOS at D806 65535 Bytes RAM 0 Bytes ROM 55302 Bytes in TPA 0 Bytes Empty 65535 Total Active Bytes Active I/O ports: 00 01 03 04 05 06 07 08 09 0A 0B 0C 0D 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF 249 Ports active
ok
2020-10-14: c2 - ada0p5 - emard/oberon - with the old values (70 Hz video refresh) I get a stable picture, and with a mouse connected (I found a Saitek Notebook Optical Mouse, model M-166) I can use Oberon a bit. Nice.
2020-10-14: c2 - ada0p5 - emard/oberon - pull to get latest fixes, then build with
$ gmake FPGA_SIZE=85
and program with
$ gmake FPGA_SIZE=85 UJPROG=fujprog program
unfortunately, my monitor doesn't like that and now I get a rolling picture.
2020-10-14: c2 - ada0p5 - lawrie/ulx3s_bit_streams - 68k/bitstreams/ulx3s_85f_68k.bit - I get a signal, but no picture / info on screen. Trying with terminal
$ fujprog -t 68k/bitstreams/ulx3s_85f_68k.bit $ fujprog -b 9600 -t 68k/bitstreams/ulx3s_85f_68k.bit
not working
2020-10-14: c2 - ada0p5 - lawrie/ulx3s_bit_streams - zxspectrum/bitstreams/zxspectrum85f.bit - works, I can program in basic (ZX Spectrum lobotomized basic, but still)
2020-10-14: c2 - ada0p5 - lawrie/ulx3s_bit_streams - zx80/bitstreams/zx90_85f.bit - my monitor shows "HDMI No signal detected!" and alternates with a black screen.
2020-10-14: c2 - ada0p5 - lawrie/ulx3s_bit_streams - vic20/bitstreams/vic20_85f.bit - works, keyboard layout is a bit strange (where is the '+' key?) but the keyboard seems to work reliably.
2020-10-14: c2 - ada0p5 - lawrie/ulx3s_bit_streams - ti99_4a/bitstreams/ulx3s_85f_ti99_4a.bit - works, but the keyboard often prints multiple characters for one key press. I cn program in basic (with a little trouble, it doesn't look like backspace is working / implemented).
2020-10-13: c2 - ada0p5 - lawrie/ulx3s_bit_streams - cpm/bitstreams/cpm_85f_sd.bit - keyboard works on serial, not on ps/2 (screen works on both, but console output goes to the one with input), serial is
tingo@kg-core2$ screen /dev/cuaU0 115200
I press space on serial and get
CP/M Boot ROM 2.0 by G. Searle BC or BW - ROM BASIC Cold/Warm X - Boot CP/M (load $D000-$FFFF) :nnnn... - Load Intel-Hex file record Gnnnn - Run loc nnnn >x Boot CP/M? Loading CP/M... CP/M BIOS 2.0 by G. Searle 2013 CP/M 2.2 (c) 1979 by Digital Research A>
nice!
2020-10-13: c2 - ada0p5 - lawrie/ulx3s_bit_streams - apple2/bitstreams/apple2_85f.bit works, I have to press the reset button, then disconnect / reconnect keyboard before it works. But I can program in basic.
2020-10-13: c2 - ada0p5 - connect to the esp32 via the (usb) serial port:
tingo@kg-core2$ screen /dev/cuaU0 115200
which gives
Welcome to MicroPython on the ESP32! For generic online docs please visit http://docs.micropython.org/ For access to the hardware use the 'machine' module: import machine pin12 = machine.Pin(12, machine.Pin.OUT) pin12.value(1) pin13 = machine.Pin(13, machine.Pin.IN, machine.Pin.PULL_UP) print(pin13.value()) i2c = machine.I2C(scl=machine.Pin(21), sda=machine.Pin(22)) i2c.scan() i2c.writeto(addr, b'1234') i2c.readfrom(addr, 4) Basic WiFi configuration: import network sta_if = network.WLAN(network.STA_IF); sta_if.active(True) sta_if.scan() # Scan for available access points sta_if.connect("<AP_name>", "<password>") # Connect to an AP sta_if.isconnected() # Check for successful connection Control commands: CTRL-A -- on a blank line, enter raw REPL mode CTRL-B -- on a blank line, enter normal REPL mode CTRL-C -- interrupt a running program CTRL-D -- on a blank line, do a soft reset of the board CTRL-E -- on a blank line, enter paste mode For further help on a specific object, type help(obj) For a list of available modules, type help('modules')
that's quite a bit. modules are
>>> help('modules') __main__ framebuf ucryptolib urandom _boot gc uctypes ure _onewire inisetup uerrno urequests _thread machine uhashlib uselect _webrepl math uhashlib usocket apa106 micropython uheapq ussl btree neopixel uio ustruct builtins network ujson utime cmath ntptime umqtt/robust utimeq dht onewire umqtt/simple uwebsocket ds18x20 sys uos uzlib esp uarray upip webrepl esp32 ubinascii upip_utarfile webrepl_setup flashbdev ucollections upysh websocket_helper Plus any modules on the filesystem
hmm, so on the filesystem? more stuff
>>> uos.uname() (sysname='esp32', nodename='esp32', release='1.12.0', version='v1.12 on 2019-12-20', machine='ESP32 module with ESP32')
current directory
>>> uos.getcwd() '/'
list files in current directory
>>> uos.listdir() ['boot.py', 'ecp5.py', 'esptool.py', 'sdraw.py', 'uftpd.py', 'wifiman.py', 'wifiman.conf', 'f32c_selftest-85.bit.gz', 'main.py.template', 'bios.bin@0x300000.img.gz', 'u-boot.bin@0x310000.img.gz', 'saxonsoc-ulx3s-linux-85.bit.gz', 'counter-85.bit.gz']
ok, some files
2020-10-13: c2 - ada0p5 - lawrie/ulx3s_bit_streams - apple1/bitstreams/apple_one_85f.bit - works, I can program in basic. This sorta work (no LF, only CR):
tingo@kg-core2$ fujprog -t apple1/bitstreams/apple_one_85f.bit [..] Terminal emulation mode, using 115200 bauds Press ENTER, ~, ? for help >~?0: 4C [..] >/ TEST // TEST /" "--" " TEST "
(the last line is various PRINT statements). Hmm, does fujprog have line end conversion?
tingo@kg-core2$ fujprog -h ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Usage: fujprog [option(s)] [bitstream_file] Valid options: -c CABLE Select USB (default) or PPI JTAG CABLE -p PORT Select USB JTAG / UART PORT (default is 0) -P TTY Select TTY port (valid only with -t or -a) -T TYPE Select TYPE of input (svf, img, bit or jed) -i identify and exit -j TARGET Select bitstream TARGET as SRAM (default) or FLASH -f ADDR Start writing to SPI flash at ADDR, optional with -j flash -s FILE Convert bitstream to SVF FILE and exit -r Reload FPGA configuration from FLASH -t Enter terminal emulation mode after completing JTAG operations -b SPEED Set baudrate to SPEED (300 to 3000000 bauds) -e FILE Send and execute a f32c (MIPS/RISCV) binary FILE -x SPEED Set binary transfer speed, optional with -e -a FILE Send a raw FILE -d debug (verbose) -D DELAY Delay transmission of each byte by DELAY ms -V display version and exit -z Force action -h This help message -l X Display messages in log fashion every <X> times -S serial Select FTDI by serial to support multiple boards -q Suppress messages
nope, doesn't look like it.
2020-10-13: c2 - ada0p5 - lawrie/ulx3s_bit_streams - amiga/bitstreams/amiga_85f_ps2kbd.bit - gives "out of range" on monitor, the same does amiga/bitstreams/amiga_12f_usbjoy.bit, amiga/bitstreams/amiga_45f.bit is for another device "Found LFE5U-85F device, but the bitstream is for LFE5U-25F."
2020-10-13: c2 - ada0p5 - lawrie/ulx3s_bit_streams - altair_8800/bitstreams/altair_8800_85f.bit like so
tingo@kg-core2$ fujprog -b 9600 -t altair_8800/bitstreams/altair_8800_85f.bit [..] Terminal emulation mode, using 9600 bauds Press ENTER, ~, ? for help .J MEMORY SIZE? TERMINAL WIDTH? WANT SIN? y WANT SIN? Y 4823 BYTES FREE BASIC VERSION 3.2 [4K VERSION] OK
ok
2020-10-13: c2 - ada0p5 - lawrie/ulx3s_bit_streams - M68k/bitstreams/m68k_85F125.bit like so
tingo@kg-core2$ fujprog -b 9600 -t M68k/bitstreams/m68k_85F125.bit ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Using USB cable: ULX3S FPGA 85K v3.0.8 Programming: 100% Completed in 6.62 seconds. Terminal emulation mode, using 9600 bauds Press ENTER, ~, ? for help 100000>? monitor commands A About zBug V1.0 B Boot from RAM [100000] -> SP [100004] ->PC C Clear memory with 0x0000 D Disassemble machine code to mnemonic E Edit memory F Fill memory with 0xFFFF H Hex dump memory J Jump to address L Load Motorola s-record N New 24-bit pointer R Register(user) display S Stack(user)'s content T Trace instruction . Modify user registers, exp .PC .D0 .A0 100000>
and M68k/bitstreams/m68k_85F133.bit also works
2020-10-13: c2 - ada0p5 - testing ready-made bitstreams from lawrie/ulx3s_bit_streams on my 85F board - jupiter_ace - the machine starts "autoprinting" the same character quite quickly.
2020-10-12: c2 - ada0p5 - example emard/oberon builds now, with the latest fixes. Build with
$ gmake FPGA_SIZE=85
(or 12, or whatever size your FPGA is). Program with
tingo@kg-core2$ gmake FPGA_SIZE=85 UJPROG=fujprog program fujprog ulx3s_85f_oberon.bit ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Using USB cable: ULX3S FPGA 85K v3.0.8 Programming: 100% Completed in 7.22 seconds.
Without an Oberon microSD card, it shows a checkered pattern on the display, but with the Oberon microSD card in, it shows a screen with a mouse pointer and the System.Log and System.Tool windows. No mouse connected yet, hard to test without it.
2020-10-11: c2 - ada0p5 - example lawrie/jupiter_ace works, the keyboard works, and 'vlist .' dumps the words. But, after a while, the machine starts repeating a character (example 't') as if a key were held down. Even if I reset the machine (using the button "PWR" near US2) the repeating continues. tried changing keyboard, same problem. But only if I am defining words? I can run 'vlist .' more than 15 times with no keyboard problem. Time varies, but eventually the machine will start repeating characters.
2020-10-11: c2 - ada0p5 - example emard/ulx3s_zx81 no picture, my monitor shows intermittent "HDMI no signal detected!" messages.
2020-10-11: c2 - ada0p5 - example emard/ulx3s_zx_spectrum - I get a screen with a copyrght message, and LEDs on the ULX3S lights up, but no reaction from the keyboard.
2020-10-11: c2 - ada0p5 - example emard/ulx3s_trs_80 works.
2020-10-11: c2 - ada0p5 - example emard/icy99 works, but the keyboard routine is flaky, it will often print more than one character for a key press, making it hard to use.
2020-10-08: c2 - ada0p5 - the ti99_2 example works
tingo@kg-core2$ yosys -q -p "synth_ecp5 -json vdp.json" tiram.v tirom.v evmvdp.v tms99000.v ps2kb.v vdp99_2.v hdmi.v hexbus.v tingo@kg-core2$ nextpnr-ecp5 --lpf-allow-unconstrained --85k --package CABGA381 --json vdp.json --lpf ulx3s.lpf --textcfg vdp.cfg Info: constraining clock net 'clk_25mhz' to 25.00 MHz Warning: IO 'wifi_gpio26' is unconstrained in LPF and will be automatically placed [..] tingo@kg-core2$ ecppack vdp.cfg vdp.bit tingo@kg-core2$ fujprog vdp.bit ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Using USB cable: ULX3S FPGA 85K v3.0.8 Programming: 100% Completed in 32.76 seconds.
with a GPDI monitor and a usb keyboard connected to US2 (using a usb micro-A to usb A cable, plus a usb-A female - female adapter). Nice! Also
tingo@kg-core2$ ecppack vdp.cfg vdp-2.bit --compress tingo@kg-core2$ ll *bit -rw-r--r-- 1 tingo tingo - 412247 Oct 8 23:59 vdp-2.bit -rw-r--r-- 1 tingo tingo - 2001901 Oct 8 23:40 vdp.bit
compress works, does it reduce programming time?
tingo@kg-core2$ fujprog vdp-2.bit ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Using USB cable: ULX3S FPGA 85K v3.0.8 Programming: 100% Completed in 6.85 seconds.
yes.
2020-10-08: c2 - ada0p5 - yosys - the ghdl plugin doesn't work:
tingo@kg-core2$ gmake yosys -p 'ghdl init.vhdl -e init; synth_ecp5 -json init.json' /----------------------------------------------------------------------------\ | | | yosys -- Yosys Open SYnthesis Suite | | | | Copyright (C) 2012 - 2020 Claire Wolf <claire@symbioticeda.com> | | | | Permission to use, copy, modify, and/or distribute this software for any | | purpose with or without fee is hereby granted, provided that the above | | copyright notice and this permission notice appear in all copies. | | | | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | | | \----------------------------------------------------------------------------/ Yosys 0.9+3617 (open-tool-forge build) (git sha1 fd306b05, gcc 9.3.0-10ubuntu2 -Os) -- Running command `ghdl init.vhdl -e init; synth_ecp5 -json init.json' -- 1. Executing GHDL. warning: ieee library directory '/__w/1/s/_packages/build_linux_x86_64/fpga-toolchain/lib/ghdl/ieee/v93/' not found error: cannot find "std" library ERROR: vhdl import failed. gmake: *** [Makefile:9: init.json] Error 1
perhaps because yosys can't find its (linux) library. I wonder if I can get yosys-plugins running on FreeBSD?
2020-10-08: c2 - ada0p5 - building the blink example with the linux toolchain works, check if fujprog can upload it
tingo@kg-core2$ fujprog ulx3s.bit ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Using USB cable: ULX3S FPGA 85K v3.0.8 Programming: 100% Completed in 4.72 seconds.
yes, that works.
2020-10-08: c2 - ada0p5 - fujprog complained about not finding the cable
tingo@kg-core2$ fujprog -i ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Cannot find JTAG cable.
check permissions
tingo@kg-core2$ ls -l /dev/ugen0.4 lrwxr-xr-x 1 root wheel 9 Oct 8 16:58 /dev/ugen0.4 -> usb/0.4.0 tingo@kg-core2$ ll /dev/usb/0.4* crw------- 1 root operator - 0x2cb Oct 8 16:58 /dev/usb/0.4.0 crw------- 1 root operator - 0x2cd Oct 8 16:58 /dev/usb/0.4.1 crw------- 1 root operator - 0x2ce Oct 8 16:58 /dev/usb/0.4.2
ok, add a devd config for it
tingo@kg-core2$ cat /usr/local/etc/devd/ulx3s.conf # allow group (operator) to access the usb connection of ulx3s notify 100 { match "system" "USB"; match "subsystem" "INTERFACE"; match "type" "ATTACH"; match "vendor" "0x0403"; match "product" "0x6015"; action "chmod g+rw /dev/$cdev"; };
then try it by unplugging and re-plugging the ulx3s, nope that didn't work, needed a service devd stop && service devd start first.
This one also works
tingo@kg-core2$ cat /usr/local/etc/devd/ulx3s.conf # allow group (operator) to access the usb connection of ulx3s notify 100 { match "system" "USB"; match "subsystem" "INTERFACE"; match "type" "ATTACH"; match "vendor" "0x0403"; match "product" "0x6015"; action "usb_devaddr=`echo $cdev | sed 's#^ugen##'` && chmod g+rw /dev/usb/${usb_devaddr}.*"; };
after restarting devd. Now fujprog works
tingo@kg-core2$ fujprog -i ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Using USB cable: ULX3S FPGA 85K v3.0.8 FPGA IDCODE: 41113043 FPGA identified SIZE: 85
good.
2020-10-08: c2 - ada0p5 - linux toolchain. I have installed the linux toolchain into
tingo@kg-core2$ cat ~/progs/fpga-toolchain/VERSION nightly-20201006
but when I tried to run some tool, I got
tingo@kg-core2$ ~/progs/fpga-toolchain/bin/yosys FATAL: kernel too old Abort trap (core dumped)
fixed by changing compat.linux.osrelease before
tingo@kg-core2$ sysctl compat.linux.osrelease compat.linux.osrelease: 2.6.32
after
tingo@kg-core2$ sysctl compat.linux.osrelease compat.linux.osrelease: 3.2.0 tingo@kg-core2$ ~/progs/fpga-toolchain/bin/yosys -V Yosys 0.9+3617 (open-tool-forge build) (git sha1 fd306b05, gcc 9.3.0-10ubuntu2 -Os)
then it is just a matter of adding ~/progs/fpga-toolchain/bin to $PATH before other (usr/local/bin) directories
2020-10-08: c2 - ada0p5 - connected up my 85K board, usbconfig says
root@kg-core2# usbconfig -d ugen0.4 ugen0.4: <FER-RADIONA-EMARD ULX3S FPGA 85K v3.0.8> at usbus0, cfg=0 md=HOST spd=FULL (12Mbps) pwr=ON (500mA)
dump device descriptor
root@kg-core2# usbconfig -d ugen0.4 dump_device_desc ugen0.4: <FER-RADIONA-EMARD ULX3S FPGA 85K v3.0.8> at usbus0, cfg=0 md=HOST spd=FULL (12Mbps) pwr=ON (500mA) bLength = 0x0012 bDescriptorType = 0x0001 bcdUSB = 0x0200 bDeviceClass = 0x0000 <Probed by interface class> bDeviceSubClass = 0x0000 bDeviceProtocol = 0x0000 bMaxPacketSize0 = 0x0008 idVendor = 0x0403 idProduct = 0x6015 bcdDevice = 0x1000 iManufacturer = 0x0001 <FER-RADIONA-EMARD> iProduct = 0x0002 <ULX3S FPGA 85K v3.0.8> iSerialNumber = 0x0003 <K00474> bNumConfigurations = 0x0001
dump config
root@kg-core2# usbconfig -d ugen0.4 dump_curr_config_desc ugen0.4: <FER-RADIONA-EMARD ULX3S FPGA 85K v3.0.8> at usbus0, cfg=0 md=HOST spd=FULL (12Mbps) pwr=ON (500mA) Configuration index 0 bLength = 0x0009 bDescriptorType = 0x0002 wTotalLength = 0x0020 bNumInterfaces = 0x0001 bConfigurationValue = 0x0001 iConfiguration = 0x0000 <no string> bmAttributes = 0x00a0 bMaxPower = 0x00fa Interface 0 bLength = 0x0009 bDescriptorType = 0x0004 bInterfaceNumber = 0x0000 bAlternateSetting = 0x0000 bNumEndpoints = 0x0002 bInterfaceClass = 0x00ff <Vendor specific> bInterfaceSubClass = 0x00ff bInterfaceProtocol = 0x00ff iInterface = 0x0002 <ULX3S FPGA 85K v3.0.8> Endpoint 0 bLength = 0x0007 bDescriptorType = 0x0005 bEndpointAddress = 0x0081 <IN> bmAttributes = 0x0002 <BULK> wMaxPacketSize = 0x0040 bInterval = 0x0000 bRefresh = 0x0000 bSynchAddress = 0x0000 Endpoint 1 bLength = 0x0007 bDescriptorType = 0x0005 bEndpointAddress = 0x0002 <OUT> bmAttributes = 0x0002 <BULK> wMaxPacketSize = 0x0040 bInterval = 0x0000 bRefresh = 0x0000 bSynchAddress = 0x0000
ok
2020-10-08: c2 - ada0p5 - fujprog
tingo@kg-core2$ which fujprog /home/tingo/bin/fujprog tingo@kg-core2$ fujprog -h ULX2S / ULX3S JTAG programmer v4.6 (git 0a4cc36 built Jul 22 2020 22:13:24) Copyright (C) Marko Zec, EMARD, gojimmypi, kost and contributors Usage: fujprog [option(s)] [bitstream_file] Valid options: -c CABLE Select USB (default) or PPI JTAG CABLE -p PORT Select USB JTAG / UART PORT (default is 0) -P TTY Select TTY port (valid only with -t or -a) -T TYPE Select TYPE of input (svf, img, bit or jed) -i identify and exit -j TARGET Select bitstream TARGET as SRAM (default) or FLASH -f ADDR Start writing to SPI flash at ADDR, optional with -j flash -s FILE Convert bitstream to SVF FILE and exit -r Reload FPGA configuration from FLASH -t Enter terminal emulation mode after completing JTAG operations -b SPEED Set baudrate to SPEED (300 to 3000000 bauds) -e FILE Send and execute a f32c (MIPS/RISCV) binary FILE -x SPEED Set binary transfer speed, optional with -e -a FILE Send a raw FILE -d debug (verbose) -D DELAY Delay transmission of each byte by DELAY ms -V display version and exit -z Force action -h This help message -l X Display messages in log fashion every <X> times -S serial Select FTDI by serial to support multiple boards -q Suppress messages
ok
2020-10-05: c2 - ada0p5 - I downloaded fujprog from latest release, it runs as well on FreeBSD as on linux.
2020-10-05: c2 - ada0p5 - pkg - ulx3s toolchain - abc is also needed
Oct 5 22:32:44 kg-core2 pkg: abc-g20200322 installed
ok
2020-10-05: c2 - ada0p5 - pkg - install toolchain for ULX3S boards: Yosys, GHDL, Boolector, Yices, Z3, Trellis, IceStorm, nextpnr, dfu-util. Not in ports: SymbiYosys, ecpprog, openFPGALoader and fujprog.
Oct 5 21:59:42 kg-core2 pkg: yosys-0.9 installed Oct 5 22:00:14 kg-core2 pkg: gcc6-aux-20180516_1,1 installed Oct 5 22:00:14 kg-core2 pkg: ghdl-0.37 installed Oct 5 22:01:40 kg-core2 pkg: picosat-965 installed Oct 5 22:01:40 kg-core2 pkg: minisat-2.2.1_2 installed Oct 5 22:01:40 kg-core2 pkg: btor2tools-g20190418 installed Oct 5 22:01:40 kg-core2 pkg: boolector-3.2.1 installed Oct 5 22:02:23 kg-core2 pkg: yices-2.6.2 installed Oct 5 22:03:27 kg-core2 pkg: z3-4.8.8 installed Oct 5 22:03:52 kg-core2 pkg: trellis-g20190422_3 installed Oct 5 22:04:28 kg-core2 pkg: icestorm-g20190526_3 installed Oct 5 22:05:10 kg-core2 pkg: nextpnr-g20191026_1 installed Oct 5 22:05:47 kg-core2 pkg: dfu-util-0.9 installed
and do a 'pkg delete -f' on hal
Oct 5 22:08:50 kg-core2 pkg: hal-0.5.14_34 deinstalled
ok